Introduction

ChipVerify Pro is an all-in-one web-based platform for learning Verilog development, offering simulation, synthesis, timing analysis, and verification tools—directly in your browser.

What Can You Do?

Quick Start

Get started in 5 minutes with this simple workflow:

1. Write Your Code

   Use the built-in Monaco editor or load templates from the "Code Templates" button.

2. Add a Testbench

   Create a file with "test" or "tb" in the name for automatic testbench detection.

3. Run Simulation

   Click the "Simulate" tab → Enable waveform → Click "Run Simulation"

4. View Waveforms

   Press Alt + W or click the waveform button to view signals.

5. Synthesize (Optional)

   Go to "Synth" tab → Select template → Run synthesis to get gate-level netlist and PPA metrics.

Site Tour

ChipVerify Pro includes an interactive guided tour to help you get familiar with all the features. The tour automatically launches when you first sign in.

What the Tour Covers

The 2-minute tour walks you through:

1. File Explorer

   Create, organize, and manage your Verilog files with the file panel.

2. Code Editor

   Monaco-powered editor with syntax highlighting, auto-completion, and error detection.

3. File Menu

   Create projects, save/load, browse examples, and download files.

4. Simulation

   Run simulations with Icarus Verilog or Verilator and view waveforms.

5. Synthesis & Analysis

   Synthesize with Yosys, explore schematics, and run timing analysis.

6. Daily Quota

   Understand FREE tier limits (20 sim/synth per day) vs PRO unlimited.

7. Customize Layout

   Drag panels, resize borders, and save custom layouts (PRO).

8. More Features

   Share projects, keyboard shortcuts, and clear outputs.

Restarting the Tour

To take the tour again at any time:

• Click the About menu in the top toolbar
• Select "Take Site Tour"

Interface Overview

Layout

The interface is divided into three main areas:

Left Sidebar Tabs

• Files - Manage Verilog files, add/delete/rename
• Simulate - Configure and run simulations
• Synth - Synthesis settings and templates
• Lint - Code quality checks
• STA - Static timing analysis settings

Right Panel Tabs

• Console - Simulation/synthesis output with search
• Lint - Verilator lint results
• Netlist - Synthesized gate-level Verilog
• Diagram - Visual schematic view
• Tree - Design hierarchy
• FSM - Finite State Machine viewer
• Cell Info - Detailed cell properties
• Connectivity - Net driver/load information
• PPA - Power, Performance, Area metrics
• STA - Timing analysis reports

Panel Details

ChipVerify Pro features multiple specialized panels for analyzing your designs. Each panel provides unique insights into your Verilog code and synthesized netlist.

Console Panel

The Console panel displays real-time output from simulation, synthesis, and lint operations.

Features:

• Real-time Output - Watch compilation and simulation logs stream live
• Search Functionality - Click the search icon to find text in output
• Queue Status - Badge shows number of pending/running jobs
• Scrollable History - Review past output without losing context

FSM Panel (State Machine Viewer)

Extract and visualize Finite State Machines from your Verilog code.

How to Use:

1. Select File

   Choose a specific Verilog file from the dropdown, or select "All files" to scan everything.

2. Click "Analyze FSM"

   The tool extracts state machines from case statements and generates a diagram.

3. Explore the Diagram

   Use zoom controls to navigate. Click states to highlight transitions.

Zoom Controls:

• + - Zoom in
• - - Zoom out
• Fit - Fit diagram to viewport
• 100% - Reset to actual size
• Clear - Remove state highlights

Cell Info Panel

View detailed information about standard cells in your synthesized design.

What It Shows:

• Instance Name - Cell instance and ABC optimization name
• Cell Type - Gate type (AND2, OR3, DFF, etc.) with function description
• Input/Output Ports - Port names and connected net names
• Fanin Cells - Cells that drive this cell's inputs
• Fanout Cells - Cells driven by this cell's outputs
• Timing Paths - Setup/hold timing with slack and delay values

Liberty Cell Characteristics:

Connectivity Panel

Analyze net connectivity to understand signal flow through your design.

What It Shows:

• Drivers - Cells that output (drive) the selected net
• Loads - Cells that consume (load) the selected net
• Net Name - The wire/signal being analyzed

How to Use:

1. Click on any net (wire) in the schematic diagram
2. The Connectivity panel updates with driver and load information
3. Click "Clear" to reset the selection

Diagram Panel (Schematic Viewer)

Interactive visual representation of your synthesized netlist.

Features:

• Pan - Click and drag to move around
• Zoom - Scroll wheel to zoom in/out
• Cell Selection - Click cells to highlight and view info
• Net Highlighting - Click nets to see connectivity
• Hierarchy Navigation - Double-click modules to descend

Tree Panel (Design Hierarchy)

Explore the hierarchical structure of your design.

• View module instantiation tree
• Expand/collapse hierarchy levels
• Click modules to navigate in schematic
• See cell counts per module

File Management

Adding Files

Click the + button in the Files panel or drag & drop .v/.sv files into the browser.

Organizing Files

File Grouping:

1. Select multiple files (hold Ctrl and click)
2. Right-click → "Create Group"
3. Name your group (e.g., "ALU", "Control Logic")

Reordering: Drag and drop files to reorder them.

File Actions

• Rename: Right-click file → Rename
• Delete: Right-click file → Delete
• Download: Save/Load button → Download options

GitHub Integration

Connect your GitHub account to import repositories and sync your ChipVerify projects with GitHub.

Connecting Your GitHub Account

1. Open Account Settings

   Click your profile icon in the top-right corner, then select "Settings".

2. Click "Connect GitHub"

   In the GitHub Integration section, click the connect button.

3. Authorize ChipVerify

   You'll be redirected to GitHub. Review the permissions and click "Authorize".

4. Connection Complete

   You'll see your GitHub username and connection date in Settings.

Importing from GitHub

Once connected, you can import Verilog files from your repositories:

1. Open Project Browser

   Click "Save/Load" → "Browse Projects"

2. Click "Import from GitHub"

   A dialog shows your available repositories.

3. Select Repository

   Choose the repository containing your Verilog files.

4. Select Branch

   Pick the branch to import from (default: main/master).

5. Import Files

   Verilog files (.v, .sv) are imported into a new ChipVerify project.

Syncing Projects

Keep your ChipVerify projects in sync with GitHub:

Linking Existing Projects

Connect an existing ChipVerify project to a GitHub repository:

1. Open your project in ChipVerify
2. Click "Save/Load" → "Link to GitHub"
3. Select the target repository and branch
4. Choose sync direction (pull from GitHub or push to GitHub)

Disconnecting GitHub

To remove your GitHub connection:

1. Go to Settings (profile icon → Settings)
2. In the GitHub Integration section, click "Disconnect"
3. Confirm the disconnection

Code Editor

Features

• Syntax Highlighting - Verilog support
• Auto-completion - Built-in IntelliSense
• Multi-file Editing - Tab-based interface
• Auto-save - Saves changes every 30 seconds

Keyboard Shortcuts in Editor

Using Templates

Click "Code Templates" button in Files panel to load pre-built modules:

• Basic gates (AND, OR, XOR)
• Flip-flops and registers
• Counters and FSMs
• Multiplexers
• Testbench template

Simulation

Choosing a Simulator

ChipVerify Pro supports two industry-standard simulators:

Select your preferred simulator from the dropdown in the "Simulate" tab.

Icarus Verilog

Traditional event-driven simulator, ideal for learning and standard Verilog designs:

• Full support for delays (#10, #5ns)
• Supports all Verilog constructs including non-synthesizable code
• Easy to debug with familiar simulation behavior
• Common compilation args: -g2005 -Wall

Verilator

High-performance cycle-accurate simulator that compiles Verilog to C++:

• Much faster execution for large designs
• Strict lint checking catches more issues
• Requires synthesizable code (no delays in design files)
• Best for designs that need fast simulation
• Common compilation args: --timing --trace

Daily Simulation Quota

ChipVerify tracks your daily simulation usage:

Your remaining quota is displayed in the Simulate tab. The indicator changes color as you approach the limit:

• Green - Plenty remaining (< 80% used)
• Yellow - Running low (80-90% used)
• Red - Almost exhausted (> 90% used)

Running a Simulation

1. Prepare Your Design

   Ensure you have at least one design file (.v) and one testbench file (with "test" or "tb" in name).

2. Configure Settings

   Go to "Simulate" tab in left sidebar:

   • Simulator: Choose Icarus Verilog or Verilator
   • Compilation Args: -g2005 -Wall (Icarus) or --timing (Verilator)
   • Compile Order: Drag files to set compilation order (if module dependencies matter)
   • Enable "Dump Waveform (VCD)" for signal viewing
3. Run Simulation

   Click "Run Simulation" or press Alt + R

4. View Real-Time Logs

   Watch compilation and simulation output stream in real-time in the Console panel. You'll see clear section headers for compilation vs simulation phases.

5. View Results

   Console output appears in right panel. Green checkmark = success!

Compilation Order Control

For designs with module dependencies, you can control the exact order files are compiled:

1. Look for the "Compile Order" panel in the Simulate tab
2. Drag and drop files to reorder them (files with dependencies should come after their modules)
3. Click the "X" button to remove files you don't want to compile
4. Click "+ Add Files" to add files back or include new ones
5. The compile order is saved with your project

Clearing Simulation Cache

ChipVerify caches simulation results to speed up repeated runs. If you've modified code but still see old results:

1. Go to the "Simulate" tab
2. Click the yellow "Clear Simulation Cache" button
3. Wait for confirmation showing how many cache entries were cleared
4. Run your simulation again for fresh results

Testbench Requirements

`timescale 1ns/1ps

module tb;
    // Your testbench signals
    reg clk, rst;
    
    // Clock generation
    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end
    
    // Stimulus
    initial begin
        rst = 1;
        #20 rst = 0;
        
        // Your test cases here
        
        #1000 $finish;  // End simulation
    end
    
    // VCD dump for waveform
    initial begin
        $dumpfile("dump.vcd");
        $dumpvars(0, tb);
    end
endmodule

Synthesis

What is Synthesis?

Synthesis converts your RTL (Register Transfer Level) Verilog code into a gate-level netlist using actual hardware cells from the SkyWater 130nm PDK.

Synthesis Workflow

1. Select Template

   Choose a synthesis strategy in the "Synth" tab:

   • Technology-Mapped (Default) - Uses SkyWater PDK liberty files
   • Generic - No technology library (faster, less accurate)
   • Speed-Optimized - Maximize frequency (uses more area)
   • Area-Optimized - Minimize chip size (slower)
   • Fast Synthesis - Quick results, minimal optimization
2. Load Template

   Click "Load" to populate Yosys commands in the editor

3. Configure Options
   • Process Corner: Choose TT (typical), FF (fast), or SS (slow)
   • PPA Analysis: Enable for power/timing/area metrics
   • Generate Schematic: Create visual diagram
4. Run Synthesis

   Click "Run Synthesis" button

5. View Results
   • Console: Yosys output log
   • Netlist: Gate-level Verilog code
   • Diagram: Visual schematic (pan/zoom enabled)
   • Tree: Design hierarchy
   • PPA: Metrics (if enabled)

Process Corners Explained

Verilator Lint

What is Lint Checking?

Lint checking analyzes your Verilog code for common mistakes, coding style issues, and potential bugs before simulation or synthesis.

Running Lint

1. Go to "Lint" tab in left sidebar
2. Optional: Add Verilator arguments (e.g., -Wall --lint-only)
3. Click "Run Verilator Lint"
4. View results in the "Lint" panel on right

What Lint Checks For

• Unused signals - Variables declared but never used
• Undriven nets - Wires without drivers
• Multiple drivers - Signals driven from multiple sources
• Width mismatches - Assignment size issues
• Combinational loops - Feedback without registers
• Case statement issues - Missing defaults, overlapping cases
• Blocking vs non-blocking - Improper assignment usage

Interpreting Results

%Warning-UNUSED: design.v:15: Signal is not used: 'temp_data'
%Warning-WIDTH: design.v:23: Operator ASSIGN expects 8 bits, got 4

Each warning shows:

• Type: UNUSED, WIDTH, UNDRIVEN, etc.
• Location: File name and line number
• Description: What's wrong

Static Timing Analysis

What is STA?

STA (Static Timing Analysis) verifies that your design meets timing requirements at a given clock frequency. It analyzes all paths through the design without running simulation.

STA Workflow

1. Run Synthesis First

   ⚠️ REQUIRED: STA analyzes the gate-level netlist from synthesis

2. Configure STA Settings

   In "STA" tab:

   • Clock Period: Target clock period in nanoseconds (e.g., 10.0 = 100 MHz)
   • Process Corner: Must match synthesis corner!
3. Edit SDC Constraints (Optional)

   Click "Edit Timing Constraints (SDC)" to customize timing requirements

4. Run STA

   Click "Run STA Analysis"

5. Analyze Results

   View timing report in STA panel:

   • Setup Slack: Positive = timing met ✅, Negative = violation ❌
   • Hold Slack: Usually passes if setup passes
   • Critical Path: Slowest path through design
   • Max Frequency: Highest achievable clock speed

Understanding Slack

Setup Slack: +1.234 ns  ✅ (TIMING MET)
Hold Slack:  +0.089 ns  ✅ (TIMING MET)

Critical Path Delay: 8.766 ns
Max Frequency: 114.1 MHz (for 10ns period)

Fixing Timing Violations

1. Reduce Clock Frequency - Easiest solution, but slower performance
2. Pipeline Design - Add register stages to break long paths
3. Use Speed-Optimized Synthesis - Trades area for speed
4. Reduce Logic Depth - Simplify combinational logic
5. Check FF Corner - Best-case conditions for max performance

Waveform Viewer

Viewing Waveforms

1. Enable "Dump Waveform (VCD)" in Simulate tab
2. Run simulation successfully
3. Press Alt + W or click waveform button
4. Waveform viewer opens at bottom of screen

Waveform Controls

• Zoom: Scroll to zoom in/out on timeline
• Pan: Click and drag to move timeline
• Measure: Click two points to measure time difference
• Signal Selection: Click signals to expand/collapse hierarchy

Troubleshooting

initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, tb);  // Dump all signals in testbench
end

PPA Analysis

What is PPA?

Power, Performance, Area - the three key metrics for evaluating chip designs.

Enabling PPA

1. Go to "Synth" tab
2. Check "Run PPA Analysis"
3. Run synthesis with a template that uses Liberty files
4. View results in "PPA" panel

Metrics Explained

📏 Area Analysis

• Total Cells: Number of standard cells used
• Chip Area: Physical silicon area (µm²)
• Cell Breakdown: Which gates are used most

⚡ Performance (Timing)

• Critical Path Delay: Longest path through design (ns)
• Max Frequency: Highest achievable clock speed (MHz)
• Logic Levels: Depth of combinational logic

🔋 Power Estimation

• Dynamic Power: Power when switching (active)
• Leakage Power: Power when idle (static)
• Total Power: Sum of dynamic + leakage

PPA History (PRO)

Track and compare PPA metrics across multiple synthesis runs to understand how your design evolves and how different optimization strategies affect results.

Enabling PPA History

1. Enable PPA Analysis

   In the Synth tab, check "Run PPA Analysis"

2. Enable History Tracking

   Check "Compare with Past Runs" option

3. Run Synthesis

   Each synthesis run is automatically saved to history

Availability

What Gets Tracked

Each synthesis run captures:

• Timestamp - When the synthesis was run
• Library & Corner - HD/HS/MS/LS/HVL and TT/FF/SS
• Area Metrics - Cells, wires, chip area (um²)
• Timing - Critical path, max frequency, slack
• Power - Dynamic, leakage, and total power (uW)
• Timing Status - Whether setup/hold constraints were met

Trend Charts

When you have 2 or more runs, trend charts appear showing:

• Max Frequency Trend - Line chart with % change indicator
• Total Area Trend - Track area growth/reduction
• Total Power Trend - Monitor power consumption changes

Arrows indicate improvement (green up) or regression (red down) compared to previous run.

Sparkline Summary Cards

Quick visual overview of all metrics with mini bar charts showing historical trends. Each card displays:

• Latest value in large font
• Percentage change from baseline
• Color-coded improvement/regression

Run History Table

Detailed tabular view of all saved runs with columns for:

• Run number and timestamp
• Library and corner settings
• Cell count and wire count
• Area, frequency, and power
• Timing met status (checkmark or X)
• Delete button to remove individual entries

Using History for Optimization

1. Establish Baseline

   Run synthesis with default settings to get baseline metrics

2. Experiment with Settings

   Try different templates (Speed-Optimized, Area-Optimized)

3. Compare Results

   Use trend charts to see which changes improved PPA

4. Iterate

   Refine your design based on the trade-offs you observe

SDC Constraints

What are SDC Files?

SDC (Synopsys Design Constraints) files define timing requirements, clock specifications, and exceptions for Static Timing Analysis.

Opening SDC Editor

• Go to STA tab → Click "Edit Timing Constraints (SDC)"
• Or press Alt + C

Common SDC Commands

1. Create Clock

# Define a 100 MHz clock (10ns period)
create_clock -name clk -period 10.0 [get_ports clk]

2. Input/Output Delays

# Data arrives 2ns after clock edge
set_input_delay -clock clk 2.0 [all_inputs]

# Data must be stable 2ns before clock edge
set_output_delay -clock clk 2.0 [all_outputs]

3. Clock Uncertainty (Jitter + Skew)

# Add 100ps margin for clock jitter
set_clock_uncertainty 0.1 [get_clocks clk]

4. False Paths (Ignore Timing)

# Reset is asynchronous, don't check timing
set_false_path -from [get_ports reset]

5. Multicycle Paths

# Multiplication can take 2 clock cycles
set_multicycle_path 2 -setup -from [get_pins mult/*]
set_multicycle_path 1 -hold -from [get_pins mult/*]

SDC Template Examples

Load templates from the SDC editor dropdown:

• Basic: Single clock domain
• Multi-Clock: Multiple clock domains with crossing constraints
• Advanced: Complex constraints with exceptions

How SDC Changes STA Results

Projects

Saving Projects

1. Sign in with your Google account (required)
2. Click "Save" button or press Ctrl + Shift + S
3. Enter a project name (e.g., "alu_design")
4. Project saved to your account ✅

Loading Projects

1. Click "Save/Load" → "Browse Projects"
2. See list of your projects and example projects
3. Click a project to load it

What Gets Saved

• ✅ All Verilog files (.v, .sv, .sdc)
• ✅ Project description
• ✅ File organization (groups, order)
• ✅ File metadata
• ❌ Simulation results (temporary)
• ❌ Waveform data (too large)

Downloading Projects

Click "Save/Load" → "Download as ZIP" to get all files locally:

• All Verilog files
• README.txt with project description
• VCD waveform (if available)
• STA report (if run)
• Synthesized netlist (if available)

Learning Sessions

Learning Sessions help you track your progress while working on a single problem or assignment. As you experiment with code changes, each simulation and synthesis run is automatically recorded, allowing you to compare results and understand how each code update affects the outcome.

Why Use Learning Sessions?

When learning digital design, you often:

• Make incremental changes to your code
• Run simulation or synthesis multiple times
• Want to compare "before" and "after" results
• Need to understand what change caused an improvement or regression

Learning Sessions automatically capture every run so you can revisit and compare previous results.

Starting a New Session

1. Click "Start New Session"

   Look for the session toolbar below the main navigation bar.

2. Enter Session Details

   Provide a title (required) and optionally:

   • Description - What you're working on
   • Learning Objectives - Goals for this session
   • Course/Assignment IDs - For academic tracking
3. Start Working

   The session toolbar shows your active session with a timer and run counter.

How Runs Are Recorded

Every time you run simulation or synthesis during an active session:

• Run Number - Auto-incremented (Run #1, Run #2, etc.)
• Input Files - Your Verilog code at the time of the run
• Output Files - Generated netlists, waveforms, logs
• UI State - Panel contents, editor position, analysis data
• Metrics - Timing, area, power (for synthesis), pass/fail status

Viewing Run History

Click the "History" button in the session toolbar to open the Run History panel.

For each run, you can see:

• Job type (Simulation, Synthesis, Lint, STA)
• Status badge (Success/Failed)
• Timestamp
• Library and corner settings (for synthesis)
• Key metrics (timing met, VCD available, etc.)

Comparing Runs

Understanding how code changes affect results is the core benefit of Learning Sessions.

Compare Files

1. In the Run History panel, click "Files" on any run
2. The panel shows a comparison with the previous run
3. See which files were added, deleted, or modified
4. View line-by-line diffs showing exactly what changed

Compare Logs

1. Click "View Log" to see the full compilation/simulation log
2. Click "Compare" to see logs from two runs side-by-side
3. Useful for understanding why one run passed and another failed

Restore Previous State

1. Click "Analyze" on any run to restore that run's state
2. The editor, schematic, waveform, and all panels restore to that point
3. Great for reviewing what your code looked like at a specific run

Session Toolbar

When a session is active, the toolbar displays:

Pausing and Resuming

• Pause - Click the pause button to stop the timer. Your session remains active but paused.
• Resume - Click resume to continue working. The timer picks up where it left off.

Pausing is useful when you take a break but want accurate time tracking.

Closing a Session

1. Click the "Close" button in the session toolbar
2. Confirm in the dialog that appears
3. The session is saved and can be resumed later

Browsing Past Sessions

1. Click "Browse Sessions" in the session toolbar (when no session is active)
2. See all your past sessions with:
   • Title and status (Active/Paused/Completed)
   • Creation date and run count
   • Success rate
3. Click a session card to load and continue it
4. Use the search box to filter by title or description

Session Actions

Use Case Example

Imagine you're debugging a counter that isn't incrementing correctly:

1. Start Session

   Create a session titled "Debug 4-bit Counter"

2. Run #1 - Initial Test

   Run simulation, see the counter stuck at 0. (Failed)

3. Run #2 - Fix Clock Edge

   Change posedge to negedge, run again. Still failing.

4. Run #3 - Fix Reset Logic

   Notice reset was inverted. Fix it, run again. Success!

5. Compare Runs

   Compare Run #2 vs Run #3 files to see exactly what fix worked.

Now you have a complete record of your debugging journey, showing what you tried and what ultimately fixed the issue.

Share Code

What is Code Sharing?

Share your Verilog code, simulation results, and waveforms with others via a unique shareable link. Perfect for asking for help, showing off your work, or collaborating with classmates!

Creating a Shareable Link

1. Prepare Your Code

   Make sure your code is working and you have simulation results you want to share.

2. Click Share Button

   Look for the "Share" button in the top toolbar (near Save/Load).

3. Configure Sharing Options

   Choose what to include:

   • ✅ Code Files - All your Verilog files
   • ✅ Simulation Output - Console logs and results
   • ✅ Waveform Data - VCD file for waveform viewing
   • ✅ Synthesis Results - Netlist and PPA metrics (if available)
4. Copy Link

   Click "Generate Link" and copy the unique URL to your clipboard.

5. Share the Link

   Send the link via email, Discord, Slack, or paste it anywhere!

Viewing Shared Code

When someone shares a link with you:

1. Click the shared link - it will open ChipVerify Pro with the shared code loaded
2. View the code in read-only mode (you can't edit the original)
3. Run simulation again to see results
4. View waveforms if they were included
5. Click "Fork This Code" or "Save As New Project" to make your own editable copy

Privacy & Permissions

Use Cases

• Getting Help: Share your broken code on forums/Discord for debugging help
• Teaching: Instructors can share working examples with students
• Portfolios: Showcase your projects to potential employers
• Code Review: Get feedback from peers on your design
• Collaboration: Multiple people can fork and iterate on a design

Account Settings

Manage your ChipVerify account, connected services, and preferences from the Settings modal.

Accessing Settings

• Click your profile icon in the top-right corner
• Select "Settings" from the dropdown menu

Account Information

View your account details:

• Email Address - The email associated with your account
• User ID - Your unique identifier (useful for support requests)
• Account Type - FREE or PRO tier

GitHub Integration

Connect or disconnect your GitHub account. See the GitHub Integration section for details.

• Connected Status - Shows GitHub username and connection date
• Connect/Disconnect - Manage the GitHub link

Appearance Settings

Customize the visual theme:

Project Limits

View your project storage limits:

Subscription & Billing

Manage your ChipVerify PRO subscription and view payment history.

FREE vs PRO Comparison

Upgrading to PRO

1. Open Settings

   Click your profile icon → Settings

2. Click "Upgrade to PRO"

   In the Subscription section, click the upgrade button

3. Complete Payment

   Enter payment details on the secure Stripe checkout page

4. Enjoy PRO Features

   Your account is upgraded immediately after payment

Managing Your Subscription

In Settings → Subscription, PRO users can:

• View Status - See if subscription is active or canceled
• Next Renewal Date - When your subscription renews
• Manage Billing - Update payment method via Stripe portal
• Cancel Subscription - End your PRO subscription

Canceling Your Subscription

1. Go to Settings → Subscription
2. Click "Cancel Subscription"
3. Confirm in the dialog that appears

Payment History

View your recent payments in the Settings modal:

• Date - When the payment was processed
• Description - What the payment was for
• Amount - Payment amount (e.g., $20.00)
• Status - Succeeded (green) or Failed (red)

The last 10 payments are displayed. For complete billing history, click "Manage Billing" to access the Stripe customer portal.

Keyboard Shortcuts

Code Templates

Verilog Templates

Click "Code Templates" button to load pre-built modules:

Basic Logic

• AND Gate - 2-input AND gate
• 2:1 Multiplexer - Parameterized mux

Sequential Logic

• D Flip-Flop - Positive edge-triggered with reset
• 4-bit Counter - Up counter with reset

State Machines

• Simple FSM - Template for state machine design

Testbenches

• Testbench Template - Complete testbench skeleton with clock generation and VCD dump

Synthesis Templates

In Synth tab, load Yosys command templates:

• Technology-Mapped - Full synthesis with SkyWater PDK
• Generic - No library, faster results
• Speed-Optimized - Maximize frequency
• Area-Optimized - Minimize chip size
• Fast Synthesis - Quick with minimal optimization

Troubleshooting

Simulation Issues

❌ "No testbench found"

Solution: Ensure filename contains "test" or "tb" (e.g., "counter_tb.v")

❌ Compilation errors

• Check syntax errors in console output
• Ensure all modules are defined
• Verify port connections match module definitions

❌ Simulation hangs (never finishes)

Solution: Add $finish; in your testbench initial block

❌ No waveform data

Solution: Add to testbench:

initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, tb);
end

❌ Seeing old simulation results after code changes

Solution: Cache may not have been invalidated. Click "Clear Simulation Cache" button in Simulate tab.

❌ Verilator simulation fails but Icarus works

Solution: Verilator is more strict and requires synthesizable code. Check for:

• Delays in non-testbench code (remove #delay from design files)
• Non-synthesizable constructs (initial blocks in modules)
• Width mismatches (Verilator is very strict about bit widths)

❌ Module not found / undefined reference errors

Solution: Files may be compiled in wrong order. Go to Simulate tab → Compile Order panel, and drag files so that module definitions come before modules that use them.

Synthesis Issues

❌ "Failed to generate netlist"

• Check Yosys template for errors
• Ensure design has no syntax errors
• Try "Generic" template first for debugging

❌ "No PPA data available"

Solution: PPA requires Liberty files - use "Technology-Mapped" template and enable "Run PPA Analysis"

STA Issues

❌ "No synthesized netlist found"

Solution: Run synthesis BEFORE STA. STA analyzes the gate-level netlist.

❌ "Corner mismatch"

Solution: Set STA corner to match synthesis corner (e.g., both TT, both FF, etc.)

❌ All slack values are zero

Solution: SDC constraints missing. Either create constraints.sdc file or let STA auto-generate them.

File Management Issues

❌ Can't delete last file

By design: At least one file is required. Add a new file before deleting.

❌ File disappeared after reload

Solution: Files are not saved until you save the project. Click "Save" before closing browser.

Frequently Asked Questions

General

Q: Do I need to install anything?

A: No! Everything runs in the browser. Tools run on our servers.

Q: Is my code private?

A: Yes. Signed-in users' projects are private. Anonymous usage is also supported.

Q: What's the file size limit?

A: Individual files should be under 1MB. Total project size under 10MB.

Features

Q: What synthesis tool is used?

A: Yosys with SkyWater 130nm PDK (open-source ASIC flow)

Q: What simulators are supported?

A: Two simulators are available:

• Icarus Verilog (iverilog) - Event-driven simulation, great for learning
• Verilator - Cycle-accurate, high-performance simulation for larger designs

You can choose between them in the Simulate tab.

Q: Can I use my own PDK?

A: Currently only SkyWater 130nm is supported.

Q: Is this suitable for tapeout?

A: ChipVerify Pro is primarily for learning and prototyping. For production tapeout, use commercial EDA tools with your foundry's PDK.

Technical

Q: Why do different synthesis templates give different STA results?

A: Different optimization strategies produce different gate-level implementations. Speed-optimized uses faster cells (more area), area-optimized uses smaller cells (slower).

Q: What's the difference between simulation and synthesis?

A: Simulation tests functionality (does it work?). Synthesis maps to hardware gates (can it be built?).

Q: Why does STA require synthesis first?

A: STA analyzes timing of the gate-level netlist (actual hardware cells). RTL code doesn't have gate delays.

Q: Can I download my synthesized netlist?

A: Yes! Click "Save/Load" → "Download as ZIP" - includes netlist, reports, and all files.

Accounts & Projects

Q: Why should I sign in?

A: Signing in enables:

• Save/load projects from any device
• Auto-save (no lost work)
• Access to synthesis, STA, and advanced features

Q: Can I share projects with others?

A: Yes! Use the "Share" button to create a shareable link that anyone can access. Shared code is read-only, but viewers can fork it to make their own editable copy. You can also use "Download as ZIP" to share files manually.

Q: How long are projects stored?

A: Projects are stored indefinitely for active accounts. Inactive for 1+ year may be archived.

Q: Why am I seeing old simulation results after changing my code?

A: Results are cached for performance. The cache should auto-invalidate when you change code, but if you're seeing stale results, click the "Clear Simulation Cache" button in the Simulate tab to force a fresh run.

Q: What's the difference between Icarus Verilog and Verilator?

A: Icarus Verilog is event-driven (traditional simulation) and works great for learning and standard testbenches. Verilator is cycle-accurate and much faster for large designs, but requires clocked testbenches. Try both and see which works better for your design!

Q: How do I control the order files are compiled?

A: In the Simulate tab, you'll see a "Compile Order" panel. Drag and drop files to reorder them. This is important when you have module dependencies - modules must be compiled before they're used.