Everything you need
The full RTL-to-GDSII flow,
built for learning
Simulation, synthesis, place & route, DRC, LVS, formal verification — the same flow used in industry, zero setup required.
RTL Simulation
Run testbenches with Icarus Verilog or Verilator. Catch bugs instantly with detailed output and signal tracing.
Icarus VerilogVerilatorVCD output
Interactive Waveforms
Inspect every signal with the integrated Surfer waveform viewer. Zoom, pan, and measure — right in the browser.
Surfer viewerVCD / FSTMulti-signal
Logic Synthesis
Synthesize to SkyWater 130nm standard cells with Yosys. Get a gate-level netlist, interactive schematic, and area report instantly.
Yosyssky130 PDKSchematic
Static Timing Analysis
Learn static timing with OpenSTA across typical, fast, and slow corners. Critical paths are highlighted in the schematic to help you understand timing.
OpenSTAPPA report3 corners
Learning Sessions
Group your runs into named sessions. Track pass/fail history, compare outputs side-by-side, and see how your design improves over time.
Run historySide-by-side diffProgress tracking
Multi-file Projects
Organize your Verilog designs across multiple files. File explorer, Monaco editor, and one-click simulation of your whole design.
File explorerMonaco editor30 projects free
Place & Route
Take your synthesized netlist all the way to a placed-and-routed layout with OpenROAD on SkyWater 130nm. Post-route STA catches timing violations before tape-out.
OpenROADPost-route STAGDSII export
DRC, LVS & Layout
View your final GDSII layout in the browser with KLayout. Run Design Rule Check and Layout vs. Schematic to catch physical violations before submission.
KLayoutDRCLVS
Formal & Coverage
Go beyond simulation with SymbiYosys formal property checking and Covered code coverage analysis. Prove your design correct, not just test it.
SymbiYosysCode coverageUVM
