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Yes — a 1-month free PRO trial with no credit card required. Start it at chipverify.com/pricing and you'll get immediate access to all Pro features including STA analysis, all synthesis libraries, hierarchy viewer, and more. After the trial you're automatically moved back to the Free tier.

Yes. Cancel at any time from Account Settings. You'll keep Pro access until the end of your current billing period, then revert to Free automatically.

We don't offer refunds, but you'll retain full Pro access until the end of your current billing period after cancelling.

Liberty files contain timing and power characteristics for standard cells. PVT corners (typical, fast, slow) let you analyse your design under different operating conditions — temperature, voltage, and process variation — so you can verify it works across real-world manufacturing tolerances.

Place & route takes your synthesized gate-level netlist and physically places standard cells on a chip floorplan, then routes the wires between them. The result is a real GDSII layout file — the same format sent to a fab for fabrication. ChipVerify uses OpenROAD on the SkyWater 130nm open-source PDK. After routing you also get post-route STA (tighter timing than pre-route) and can run DRC and LVS to verify the layout is manufacturing-ready.

DRC (Design Rule Check) verifies that your layout obeys the physical manufacturing rules of the PDK — minimum wire widths, spacing, enclosures, etc. LVS (Layout vs. Schematic) checks that the physical layout matches the intended circuit schematic. Both must pass before a design is considered tape-out ready. ChipVerify runs DRC and LVS using KLayout with the SkyWater 130nm rule deck.