module lshift_reg (
    input            clk,
    input            rstn,
    input      [7:0] load_val,
    input            load_en,
    output reg [7:0] op
);

    integer i; 

    always @ (posedge clk) begin
        if (!rstn) begin
            op <= 8'b0;
        end else if (load_en) begin
            op <= load_val;
        end else begin
            // Fix: loop only to 6 so i+1 never hits 8
            for (i = 0; i < 7; i = i + 1) begin
                op[i+1] <= op[i];
            end
            op[0] <= op[7];
        end
    end

endmodule

module tb;
  reg clk;
  reg rstn;
  reg [7:0] load_val;
  reg load_en;
  wire [7:0] op;
  
  always #10 clk = ~clk;
  
  lshift_reg u0 ( .clk(clk),
                 .rstn (rstn),
                 .load_val (load_val),
                 .load_en (load_en),
                 .op (op));
  
  initial begin
    clk <= 0;
    rstn <= 0;
    load_val <= 8'h01;
    load_en <= 0;
    
    repeat (2) @ (posedge clk);
    rstn <= 1;
    repeat (5) @ (posedge clk);
    load_en <= 1;
    repeat(1) @ (posedge clk);
    load_en <= 0;
    repeat (20) @ (posedge clk);
    $finish;
  end
  
  initial begin
    $dumpvars;
    $dumpfile ("dump.vcd");
  end
endmodule