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assign statement

Verilog Assignments

Examples of how 'assign' statements can be written

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Related tutorial:
design.v
module xyz (input [3:0] x,
        input y,
        output [4:0] z);
  
  wire [1:0] a;
  wire b;

`ifdef CASE1
  	assign z = {x, y};
`elsif CASE2
  	assign z[3:1] = {x, y};
`elsif CASE3
	assign z[3:1] = {x, y};
	assign z[4] = 1;
`elsif CASE4
	assign z[3:1] = {x, y};
	assign z[3] = 0;
`elsif CASE5
	assign z[3:1] = {x, y};
	assign z[3] = 1;
`elsif CASE6
	assign z = {x[1:0], y};
`elsif CASE7
	assign z[2:0] = {x[1:0], y};
`elsif CASE8
	assign z = {3{y}};
`elsif CASE9
  	assign {a, b} = {x, y};
`elsif CASE10
  	assign {b, a} = {x, y};
`endif
  
endmodule
testbench.v
module tb;
  reg [3:0] x;
  reg y;
  wire [4:0] z;
  xyz u0 (x, y, z);
  
  initial begin
    x = 'hC;
    y = 1;
    #1;
    
    $display("z=%b", z);
    $display("a=%b b=%b", u0.a, u0.b);
  end
endmodule
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