`include "uvm_macros.svh"
import uvm_pkg::*;

class my_seq_item extends uvm_sequence_item;
  rand bit [3:0] data;

  `uvm_object_utils_begin (my_seq_item)
    `uvm_field_int(data, UVM_ALL_ON)
  `uvm_object_utils_end

  function new (string name = "my_seq_item");
    super.new(name);
  endfunction
endclass

class my_auto_sequence extends uvm_sequence #(my_seq_item);
  `uvm_object_utils (my_auto_sequence)

  
  rand int  	num_items = 5;
  
  constraint c_num_items { num_items > 0; num_items <= 20; }

  function new (string name = "my_auto_sequence");
    super.new(name);
    // Enable automatic phase objection handling
    // UVM will automatically raise an objection when the sequence starts
    // and drop it when it finishes
    
    set_automatic_phase_objection(1);
  endfunction

  virtual task body();
    `uvm_info (get_type_name(), $sformatf("sequence started"), UVM_MEDIUM)

    // No explicit raise_objection or drop_objection calls are needed here,
    // as they are handled automatically by the base class
    repeat (num_items) begin            
      #10; // Simulate some time passing between transactions
    end

    `uvm_info (get_type_name(), $sformatf("sequence ended"), UVM_MEDIUM)
  endtask
endclass  

class my_test extends uvm_test;
  `uvm_component_utils(my_test)
  
  function new(string name="my_test", uvm_component parent=null);
    super.new(name, parent);
  endfunction
  
  virtual task run_phase(uvm_phase phase);        
    my_auto_sequence 	l_seq = my_auto_sequence::type_id::create("l_seq");
    
    super.run_phase(phase);    
    `uvm_info(get_type_name(), $sformatf("my_test started"), UVM_MEDIUM)
      
    l_seq.set_starting_phase(phase);
    l_seq.start(null);

    `uvm_info(get_type_name(), $sformatf("my_test ended"), UVM_MEDIUM)
  endtask 
  
endclass
      
module tb;
  reg clk;
  
  always #10 clk = ~clk;
  
  initial begin
    clk = 0;
    run_test("my_test");
  end
endmodule

// Code your design here