// Design under test
module des (input logic clk, req, output logic gnt);
  always @(posedge clk)
    gnt <= req;
endmodule

// Interface with a clocking block
interface req_gnt_if (input logic clk);
  logic req;
  logic gnt;

  clocking cb @(posedge clk);
    default input #1step output #1ns;
    input  gnt;   // testbench reads: comes from design
    output req;   // testbench drives: goes into design
  endclocking
endinterface

// Testbench
module tb;
  logic clk;

  // Generate a 10ns clock (posedge at 0, 10, 20 ...)
  initial clk = 0;
  always #5 clk = ~clk;

  // Instantiate the interface and the design
  req_gnt_if vif (.clk(clk));
  des dut (.clk(clk), .req(vif.req), .gnt(vif.gnt));

  initial begin
    // Drive req through the clocking block
    vif.cb.req <= 0;

    @(vif.cb);          // wait for one clock edge
    vif.cb.req <= 1;    // assert request

    @(vif.cb);          // wait one more clock
    $display("gnt = %b", vif.cb.gnt);  // read grant

    @(vif.cb);
    vif.cb.req <= 0;

    #20 $finish;
  end
endmodule