module des (input logic req, clk, output logic gnt);
  always @(posedge clk)
    gnt <= req ? 1 : 0;
endmodule

interface req_gnt_if (input logic clk);
  logic gnt;
  logic req;

  clocking cb @(posedge clk);
    input  #1ns gnt;   // sample gnt 1ns before posedge
    output #5ns req;   // drive  req 5ns after  posedge
  endclocking
endinterface

module tb;
  logic clk;

  logic req_v;   // local copy of the value driven on req (Verilator cannot read an output clockvar)

  initial clk = 0;
  always #10 clk = ~clk;   // 20ns period, posedge at 0, 20, 40 ...

  req_gnt_if vif (.clk(clk));
  des dut (.clk(clk), .req(vif.req), .gnt(vif.gnt));

  always @(vif.cb) $display("[%0t] req=%b gnt=%b", $time, req_v, vif.cb.gnt);

  initial begin
    req_v = 0;
    vif.cb.req <= req_v;

    // Toggle req several times at random intervals
    repeat (5) begin
      repeat ($urandom_range(1,3)) @(vif.cb);
      req_v = ~req_v;
      vif.cb.req <= req_v;
    end

    #40 $finish;
  end
endmodule