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Combinational Logic with assign: Testbench

Verilog Examples

Runnable example from the Combinational Logic with assign tutorial (Testbench)

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design.v
module fa (	input 	a, b, cin,
						output 	sum, cout);

	// Sum: XOR chain handles the three-input addition
	// Result is 1 when odd number of inputs are 1
	assign sum = (a ^ b) ^ cin;

	// Carry out: Generate carry when (a AND b) OR when sum of a,b generates carry with cin
	// This is the standard full adder carry equation
	assign cout = (a & b) | ((a ^ b) & cin);
endmodule
testbench.v
module tb;
	reg a, b, cin; // Three input bits for full adder
	wire sum, cout; // Sum and carry outputs
	integer i;

	fa u0 ( .a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));

	initial begin
		a = 0;
		b = 0;

		$monitor("a=%0b b=%0b cin=%0b sum=%0b cout=%0b", a, b, cin, sum, cout);

		// Test all 8 combinations (2^3 = 8)
		for (i = 0; i < 8; i = i + 1) begin
			{a, b, cin} = i;
			#10;
		end
	end
endmodule
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