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`define without default arguments

SystemVerilog Advanced Features

Runnable example from the SystemVerilog `define Macro tutorial (`define without default arguments)

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testbench.sv
`define   ADD(name, a, b)    $display("%s a=%0d b=%0d sum=%0d", name, a, b, a + b);

module tb;
  
  bit [3:0]   a;
  bit [3:0]   b;
  
  initial begin
    std::randomize(a, b);    
    
    // The macro below will be replaced by the display statement
    // Remember ! `define is not a function, it is text substitution
    // before compilation
    `ADD("", a, b)
        
    // ERROR ! Hierarchical name component lookup failed for 'ADDR' at 'tb'
    // First argument in the display statement requires it to be a string
    // `ADD(ADDR, a, b)
    
    // Text substitute a with 3 and b with 4
    `ADD("ADDER", 3, 4)
    
    // Notice the extra space in the first argument
    `ADD(" INST ", 3, 4)
    
    // ERROR ! Macro is missing trailing arguments that have no default values
    // 'b' does not have a default argument and none is passed during macro call
    //`ADD(3, )
    
    // ERROR ! Macro is missing trailing arguments that have no default values (1 instead of 3)
    // `ADD(5)
    
    // ERROR ! Too many actual macro arguments (4 instead of 3)
    //`ADD("STH", 4, 5, 6)    
    
    // Whitespace between `ADD and (
    `ADD ("SPACE", 1, 1)
  end  
endmodule
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