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Edge Sensitive UDP

Verilog Advanced Topics

Edge Sensitive UDP — a ready-to-run Verilog example.

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design.v
primitive d_flop (q, clk, d);
	output  q;
	input 	clk, d;
	reg 	q;
	
	table
		// clk 		d 	 	q 		~q
			// obtain output on risind edge of clk
			(01)	0 	: 	? 	: 	0;
			(01) 	1 	: 	? 	: 	1;
			(0?) 	1 	: 	1 	: 	1;
			(0?) 	0 	: 	0 	: 	0;
			
			// ignore negative edge of clk
			(?0) 	? 	: 	? 	: 	-;
			
			// ignore data changes on steady clk
			? 		(??): 	? 	: 	-;
	endtable
endprimitive
testbench.v
module tb;
  reg clk, d;
  reg [1:0] dly;
  wire q;
  integer i;
  
  d_flop u_flop (q, clk, d);
  
  always #10 clk = ~clk;
  
  initial begin
    clk = 0;
    
    $monitor ("[T=%0t] clk=%0b d=%0b q=%0b", $time, clk, d, q); 
    
    #10;
    
    for (i = 0; i < 20; i = i+1) begin
      dly = $random;
      repeat(dly) @(posedge clk);
      d <= $random;
    end
    
    #20 $finish;
  end
  
  initial begin
    $dumpvars;
    $dumpfile("dump.vcd");
  end
endmodule
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