`include "uvm_macros.svh"
import uvm_pkg::*;

class my_seq_item extends uvm_sequence_item;
  rand bit [3:0] data;

  `uvm_object_utils_begin (my_seq_item)
    `uvm_field_int(data, UVM_ALL_ON)
  `uvm_object_utils_end

  function new (string name = "my_seq_item");
    super.new(name);
  endfunction
endclass

// Define a UVM sequence
class my_sequence extends uvm_sequence #(my_seq_item);
  `uvm_object_utils (my_sequence) 

  rand int num_items = 5; // Number of items this sequence will generate
  constraint c_num_items { num_items > 0; num_items <= 20; } 

  function new (string name = "my_sequence");
    super.new(name);
  endfunction

  virtual task body();
    // Get a handle to the phase in which this sequence was started.
    // The 'starting_phase' member variable is automatically set when the sequence is started as a default sequence.
    // If started manually, the test can set it explicitly.
    uvm_phase phase = get_starting_phase();

    // Check if the phase handle is valid before raising/dropping objections
    if (phase != null) begin
      // Raise an objection to prevent the current phase from ending
      // 'this' refers to the current sequence instance
      // The description "Sequence generating stimulus" helps with debugging 
      phase.raise_objection(this, "Sequence generating stimulus");
    end

    // Core activity of the sequence
    repeat (num_items) begin
      #10; // Simulate some time passing between transactions
    end

    if (phase != null) begin
      // Drop the objection, indicating that the sequence's activity in this phase is complete
      phase.drop_objection(this, "Sequence finished stimulus generation");
    end
  endtask
endclass

class my_test extends uvm_test;
  `uvm_component_utils(my_test)
  
  function new(string name="my_test", uvm_component parent=null);
    super.new(name, parent);
  endfunction
  
  virtual task run_phase(uvm_phase phase);        
    my_sequence 	l_seq = my_sequence::type_id::create("l_seq");
    
    super.run_phase(phase);    
    `uvm_info(get_type_name(), $sformatf("my_test started"), UVM_MEDIUM)
      
    l_seq.set_starting_phase(phase);
    l_seq.start(null);

    `uvm_info(get_type_name(), $sformatf("my_test ended"), UVM_MEDIUM)
  endtask 
  
endclass
      
module tb;
  reg clk;
  
  always #10 clk = ~clk;
  
  initial begin
    clk = 0;
    run_test("my_test");
  end
endmodule

// Code your design here