interface bus_if (input logic clk);
  logic       write;
  logic       sel;
  logic [7:0] data;
endinterface

class Monitor;
	virtual bus_if vif;

	function new (virtual bus_if vif);
		this.vif = vif;
	endfunction

	virtual task run();
		forever begin
			@(posedge vif.clk);
			if (vif.write & vif.sel)
				$display ("[%0t] Capture write data = 0x%0h", $time, vif.data);
			if (!vif.write & vif.sel)
				$display ("[%0t] Capture read data  = 0x%0h", $time, vif.data);
		end
	endtask
endclass

module tb;
	logic clk = 0;
	always #5 clk = ~clk;

	bus_if  bus (clk);
	Monitor mon = new(bus);

	// Start the monitor task and allow it to continue as
	// long as there is activity on the bus
	initial begin
		fork
			mon.run();
		join_none
	end

	// Some bus activity
	initial begin
		bus.sel = 0; bus.write = 0; bus.data = 0;
		#12 bus.sel = 1; bus.write = 1; bus.data = 8'hA5;
		#10 bus.write = 0; bus.data = 8'h3C;
		#10 bus.sel = 0;
		#20 $finish;
	end
endmodule