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ifdef Design Example

Verilog Conditional Compilation

Use ifdef to include the code only if the macro is defined in compilation args

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design.v
module my_design (input clk, d, 

`ifdef INCLUDE_RSTN
                  input rstn,
`endif                  
                  output reg q);
  
  always @ (posedge clk) begin
      
`ifdef INCLUDE_RSTN
    if (!rstn) begin
      q <= 0;
    end else     
`endif
    begin
      q <= d;
    end
  end
endmodule
testbench.v
module tb;
  reg clk, d, rstn;
  wire q;
  reg [3:0] delay;
  
  my_design u0 ( .clk(clk), .d(d),
`ifdef INCLUDE_RSTN
                .rstn(rstn),
`endif
                .q(q));
  
  always #10 clk = ~clk;
  
  initial begin
    integer i;
    
    {d, rstn, clk} <= 0;

    for (i = 0 ; i < 10; i=i+1) begin
      delay = $random;
      #(delay) d <= $random;
    end
    
	#20 rstn <= 1;    

    for (i = 0 ; i < 10; i=i+1) begin
      delay = $random;
      #(delay) d <= $random;
    end
    
    #20 $finish;
  end
  
  initial begin
    $dumpvars;
    $dumpfile ("dump.vcd");
  end
endmodule
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