interface _if (input logic clk);
  logic req;

  clocking cb_0 @(posedge clk);
    output #0ns req;    // driven in Re-NBA region (same edge)
  endclocking

  clocking cb_1 @(posedge clk);
    output #2ns req;    // driven 2ns after posedge
  endclocking

  clocking cb_2 @(posedge clk);
    output #5ns req;    // driven 5ns after posedge
  endclocking
endinterface

module my_des (my_if _if);
  
  always @ (posedge _if.clk) begin
    if (_if.push) begin
    	// Immediate assertion and ensures that
    	// fifo is not full when push is 1
    	a_push: assert (!_if.full) begin
      		$display("[PASS] push when fifo not full");
    	end else begin
      		$display("[FAIL] push when fifo full !");
    	end
  	end
  
    if (_if.pop) begin
    	// Immediate assertion to ensure that fifo is not
    	// empty when pop is 1
    	a_pop: assert (!_if.empty) begin
      		$display ("[PASS] pop when fifo not empty");
    	end else begin
      		$display ("[FAIL] pop when fifo empty !");
    	end
    end
  end
endmodule

interface my_if(input bit clk);
  logic pop;
  logic push;
  logic empty;
  logic full;
endinterface

module tb;
  bit clk;
  always #10 clk <= ~clk;
  
  my_if _if (clk);  
  my_des u0 (.*);
  
  initial begin
    for (int i = 0; i < 5; i++) begin
      _if.push  <= $random;
      _if.pop   <= $random;
      _if.empty <= $random;
      _if.full  <= $random;
      $strobe("[%0t] push=%0b full=%0b pop=%0b empty=%0b",
              $time, _if.push, _if.full, _if.pop, _if.empty);
      @(posedge clk);
    end
    #10 $finish;
  end  
endmodule