// "dff" is the name of this module

module dff  ( input   d,            // Inputs to the design should start with "input"
                      rstn,
                      clk,
              output reg q);         // Outputs of the design should start with "output"

  always @ (posedge clk) begin      // This block is executed at the positive edge of clk 0->1
    if (!rstn)                      // At the posedge, if rstn is 0 then q should get 0
      q <= 0;
    else
      q <= d;                       // At the posedge, if rstn is 1 then q should get d
  end
endmodule                           // End of module

module tb;

  // 1. Declare input/output variables to drive to the design
  reg   tb_clk;
  reg   tb_d;
  reg   tb_rstn;
  wire  tb_q;

  // 2. Create an instance of the design
  // This is called design instantiation
  dff   dff0 ( .clk   (tb_clk),     // Connect clock input with TB signal
               .d     (tb_d),       // Connect data input with TB signal
               .rstn  (tb_rstn),    // Connect reset input with TB signal
               .q     (tb_q));      // Connect output q with TB signal

  // 3. The following is an example of a stimulus
  // Here we drive the signals tb_* with certain values
  // Since these tb_* signals are connected to the design inputs,
  // the design will be driven with the values in tb_*
  initial begin
    tb_rstn <= 1'b0;    // Start with reset asserted (active-low)
    tb_clk  <= 1'b0;    // Initialize clock to 0
    tb_d    <= 1'b0;    // Initialize data input to 0
  end
endmodule