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Johnson Counter

Verilog Counters

Example of a Johnson Counter

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Related tutorial:
design.v
module johnson_ctr #(parameter WIDTH=4) 
  (  
	input clk,                
	input rstn,
  	output reg [WIDTH-1:0] out
  );

  reg [$clog2(WIDTH):0] i;
 
  always @ (posedge clk) begin
      if (!rstn)
         out <= 1;
      else begin
        out[WIDTH-1] <= ~out[0];
        for (i = 0; i < WIDTH-1; i=i+1) begin
          out[i] <= out[i+1];
        end
      end
  end
endmodule
testbench.v
module tb;
    parameter WIDTH = 4;
  
    reg clk;
    reg rstn;
    wire [WIDTH-1:0] out;
  
    johnson_ctr 	u0 (.clk (clk),
                        .rstn (rstn),
                        .out (out));
  
    always #10 clk = ~clk;
  
    initial begin
        {clk, rstn} <= 0;

        $monitor ("T=%0t out=%b", $time, out);
        repeat (2) @(posedge clk);
        rstn <= 1;
        repeat (15) @(posedge clk);
        $finish;
    end
  
endmodule
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