// Module called "dff" has 3 inputs and 1 output port
module dff ( 	input 		d,       // Data input
				input 		clk,     // Clock signal
				input 		rstn,    // Active-low asynchronous reset
				output reg	q);      // Registered output (must be 'reg' for sequential logic)

	// Sequential logic block: executes on every positive clock edge
	always @ (posedge clk) begin
		if (!rstn)             // Reset condition (active-low: rstn=0 triggers reset)
			q <= 0;              // Non-blocking assignment: reset output to 0
		else
			q <= d;              // Non-blocking assignment: capture input data
	end
endmodule

// 4-bit shift register built from four DFF module instances
module shift_reg ( 	input 	d,       // Serial data input
					input 	clk,     // Clock signal shared by all DFFs
					input 	rstn,    // Reset signal shared by all DFFs
					output 	q);      // Serial data output (final stage)

	// Internal wires connecting adjacent DFF stages
	wire [2:0] q_net;  // q_net[0] = u0 output, q_net[1] = u1 output, q_net[2] = u2 output

	// Module instantiation using named port mapping
	dff u0 (.d(d),          .clk(clk), .rstn(rstn), .q(q_net[0]));  // Stage 0: input -> q_net[0]
	dff u1 (.d(q_net[0]),   .clk(clk), .rstn(rstn), .q(q_net[1]));  // Stage 1: q_net[0] -> q_net[1]
	dff u2 (.d(q_net[1]),   .clk(clk), .rstn(rstn), .q(q_net[2]));  // Stage 2: q_net[1] -> q_net[2]
	dff u3 (.d(q_net[2]),   .clk(clk), .rstn(rstn), .q(q));         // Stage 3: q_net[2] -> output

endmodule

// Enter testbench code