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Operator

SystemVerilog Assertions

An SVA sequence using the ##2 cycle-delay operator (a ##2 b) inside an assert property sampled on every clock edge.

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testbench.sv
module tb;
  bit a, b;
  bit clk;
  
  // This is a sequence that says 'b' should be high 2 clocks after
  // 'a' is found high. The sequence is activated on every positive
  // edge of the clock which ultimately ends up having multiple 
  // assertions running in parallel since they all span for more
  // than a single clock cycle.
  sequence s_ab;
    @(posedge clk) a ##2 b;
  endsequence
  
  assert property(s_ab) $display ("[%0t] Assertion passed !", $time);
  
  always #10 clk = ~clk;
  
  initial begin
    for (int i = 0; i < 10; i++) begin      
      @(posedge clk);
      a <= $random;
      b <= $random;                    
      
      $display("[%0t] a=%b b=%b", $time, a, b);
    end
    
    #20 $finish;
  end
    
  initial begin
    $dumpvars;
    $dumpfile("dump.vcd");
  end
  
endmodule
design.sv
// Code your design here
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