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PD: 32-bit Adder, Two Pipeline Stages

Verilog Physical Design

The same adder split into two stages of 16 bits (146 flip-flops). Closes at 5 ns in the lab flow, 4 ns with a setup margin.

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Related tutorial:
design.v
module add32p (
  input             clk,
  input      [31:0] a,
  input      [31:0] b,
  output reg [32:0] s
);
  reg [31:0] ra, rb;
  reg [16:0] lo;          // stage 1: low half and its carry
  reg [15:0] ha, hb;      // stage 1: high halves, delayed one cycle

  always @(posedge clk) begin
    ra <= a;
    rb <= b;
    lo <= ra[15:0] + rb[15:0];
    ha <= ra[31:16];
    hb <= rb[31:16];
    s  <= {{1'b0, ha} + hb + lo[16], lo[15:0]};   // stage 2: high half, 17 bits wide
  end
endmodule
constraints.sdc
# Synthesis STA constraints. Place and Route takes its clock period from the panel (try 4 ns and 5 ns).
create_clock -name clk -period 5 [get_ports clk]
set_input_delay  1.0 -clock clk [get_ports {a* b*}]
set_output_delay 1.0 -clock clk [get_ports {s*}]
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