// The SRAM macro is a black box for synthesis; place and route reads its LEF and Liberty.
(* blackbox *)
module sky130_sram_1rw1r_44x64_8 (
  input         clk0,
  input         csb0,
  input         web0,
  input  [5:0]  wmask0,
  input  [5:0]  addr0,
  input  [43:0] din0,
  output [43:0] dout0,
  input         clk1,
  input         csb1,
  input  [5:0]  addr1,
  output [43:0] dout1
);
endmodule

module sram_wrap (
  input             clk,
  input             we,
  input      [5:0]  addr,
  input      [43:0] din,
  output reg [43:0] dout,
  output reg        parity
);
  reg        we_q;
  reg [5:0]  addr_q;
  reg [43:0] din_q;
  wire [43:0] rdata;

  always @(posedge clk) begin
    we_q   <= we;
    addr_q <= addr;
    din_q  <= din;
  end

  sky130_sram_1rw1r_44x64_8 u_sram (
    .clk0   (clk),
    .csb0   (1'b0),
    .web0   (~we_q),
    .wmask0 (6'h3f),
    .addr0  (addr_q),
    .din0   (din_q),
    .dout0  (rdata),
    .clk1   (clk),
    .csb1   (1'b1),
    .addr1  (6'd0),
    .dout1  ()
  );

  always @(posedge clk) begin
    dout   <= rdata ^ {rdata[21:0], rdata[43:22]};
    parity <= ^rdata;
  end
endmodule

create_clock -name clk -period 10.0 [get_ports clk]
set_input_delay 2.0 -clock clk [get_ports {we addr* din*}]
set_output_delay 2.0 -clock clk [get_ports {dout* parity}]