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PD: UART Transmitter (reset synchronizer, no tie cells needed)

Verilog Physical Design

A 115200-baud UART transmitter with a two-flop reset synchronizer: 27 flip-flops, about 1,200 um2. Routes in the lab at 10 ns down to about 2 ns.

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design.v
module uart_tx (
  input        clk,
  input        rst_n,
  input        start,
  input  [7:0] data,
  output reg   tx,
  output       busy
);
  // baud divider: 28 x 31 = 868 clocks per bit (100 MHz / 115200)
  reg [4:0] ca, cb;
  reg [3:0] bit_idx;
  reg [7:0] shreg;
  reg       active;
  reg       tick;                      // registered: high while ca == 27 and cb == 30
  assign busy = active;
  // reset synchronizer: reset asserts at once, releases on a clock edge
  reg rs1, rs2;
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      rs1 <= 1'b0;
      rs2 <= 1'b0;
    end
    else begin
      rs1 <= rst_n;   // samples the (released) reset: no constant input, so no tie cell needed
      rs2 <= rs1;
    end
  end
  wire rst_s = rs2;
  always @(posedge clk or negedge rst_s) begin
    if (!rst_s) begin
      ca <= 5'd0;
      cb <= 5'd0;
      bit_idx <= 4'd0;
      shreg <= 8'd0;
      active <= 1'b0;
      tx <= 1'b1;
      tick <= 1'b0;
    end
    else begin
      tick <= active && (ca == 5'd26) && (cb == 5'd30);
      if (!active) begin
        ca <= 5'd0;
        cb <= 5'd0;
        tx <= 1'b1;
        if (start) begin
          active <= 1'b1;
          shreg <= data;
          bit_idx <= 4'd0;
          tx <= 1'b0;
        end
      end
      else begin
        if (ca == 5'd27) begin
          ca <= 5'd0;
          cb <= (cb == 5'd30) ? 5'd0 : cb + 5'd1;
        end
        else
          ca <= ca + 5'd1;
        if (tick) begin
          if (bit_idx == 4'd8) begin
            tx <= 1'b1;
            bit_idx <= bit_idx + 4'd1;
          end
          else if (bit_idx == 4'd9) begin
            active <= 1'b0;
          end
          else begin
            tx <= shreg[0];
            shreg <= {1'b0, shreg[7:1]};
            bit_idx <= bit_idx + 4'd1;
          end
        end
      end
    end
  end
endmodule
constraints.sdc
# Synthesis STA constraints. Place and Route takes its clock period from the panel (start with 10 ns).
create_clock -name clk -period 10 [get_ports clk]
set_input_delay  2.0 -clock clk [get_ports {start data*}]
set_output_delay 2.0 -clock clk [get_ports {tx busy}]
# The external reset is released through the two-flop synchronizer, so it is not timed.
set_false_path -from [get_ports rst_n]
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