SoC Design: Boot C on cvsoc

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Compile C for RISC-V and boot it on cvsoc: the cvr32 core with a TCM, an AXI4-Lite interconnect, SRAM, UART, timer and GPIO. All the RTL is here to read and change. Press Run Simulation: the program prints over the UART to the Console.

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main.c

/* main.c: runs on the cvsoc SoC. The program loads into the TCM, and SRAM, the UART
   and GPIO are reached over the bus. cvsoc.h has the register addresses and drivers. */
#include "cvsoc.h"

int main(void)
{
    volatile u32 *sram = (volatile u32 *)SRAM_BASE;
    u32 sum = 0;

    uart_puts("Booted on cvsoc\n");
    for (u32 i = 0; i < 8; i++)
        sram[i] = i * i;
    for (u32 i = 0; i < 8; i++)
        sum += sram[i];

    uart_puts("sum: 0x");
    uart_hex(sum);
    uart_putc('\n');
    GPIO_OUT = sum;
    uart_wait_idle();
    return sum;
}

cvsoc.h

/* cvsoc memory map and tiny drivers. No C library. */
typedef unsigned int u32;

#define SRAM_BASE   0x20000000u
#define UART_BASE   0x40000000u
#define TIMER_BASE  0x40001000u
#define GPIO_BASE   0x40002000u

#define REG(a)      (*(volatile u32 *)(a))
#define UART_TXDATA REG(UART_BASE + 0x0)
#define UART_STATUS REG(UART_BASE + 0x4)
#define UART_DIV    REG(UART_BASE + 0x8)
#define TIMER_LO    REG(TIMER_BASE + 0x0)
#define GPIO_OUT    REG(GPIO_BASE + 0x0)
#define GPIO_IN     REG(GPIO_BASE + 0x4)

static inline u32 xs32(u32 *s)
{
    u32 x = *s;
    x ^= x << 13;
    x ^= x >> 17;
    x ^= x << 5;
    *s = x;
    return x;
}

#ifndef HOST
static void uart_putc(char c)
{
    while (UART_STATUS & 1)            /* wait while the FIFO is full */
        ;
    UART_TXDATA = (u32)c;
}

static void uart_puts(const char *s)
{
    while (*s)
        uart_putc(*s++);
}

static void uart_hex(u32 v)
{
    for (int i = 28; i >= 0; i -= 4) {
        u32 d = (v >> i) & 0xF;
        uart_putc(d < 10 ? '0' + d : 'a' + d - 10);
    }
}

static void uart_wait_idle(void)
{
    while (UART_STATUS & 2)            /* bytes queued or still sending */
        ;
}
#endif

cvr32_alu.sv

// cvr32_alu: the integer ALU of the cvr32 core (RV32I)
module cvr32_alu (
    input  logic [3:0]  op,      // operation, one of the ALU_* codes below
    input  logic [31:0] a,       // first operand (rs1, PC or zero)
    input  logic [31:0] b,       // second operand (rs2 or immediate)
    output logic [31:0] y        // result
);

    localparam logic [3:0] ALU_ADD  = 4'd0;
    localparam logic [3:0] ALU_SUB  = 4'd1;
    localparam logic [3:0] ALU_SLL  = 4'd2;
    localparam logic [3:0] ALU_SLT  = 4'd3;
    localparam logic [3:0] ALU_SLTU = 4'd4;
    localparam logic [3:0] ALU_XOR  = 4'd5;
    localparam logic [3:0] ALU_SRL  = 4'd6;
    localparam logic [3:0] ALU_SRA  = 4'd7;
    localparam logic [3:0] ALU_OR   = 4'd8;
    localparam logic [3:0] ALU_AND  = 4'd9;

    always @(*) begin
        case (op)
            ALU_ADD:  y = a + b;
            ALU_SUB:  y = a - b;
            ALU_SLL:  y = a << b[4:0];                       // shift amount is the low 5 bits
            ALU_SLT:  y = {31'd0, $signed(a) < $signed(b)};
            ALU_SLTU: y = {31'd0, a < b};
            ALU_XOR:  y = a ^ b;
            ALU_SRL:  y = a >> b[4:0];
            ALU_SRA:  y = $unsigned($signed(a) >>> b[4:0]);  // arithmetic shift keeps the sign
            ALU_OR:   y = a | b;
            ALU_AND:  y = a & b;
            default:  y = a + b;
        endcase
    end

endmodule

cvr32_regfile.sv

// cvr32_regfile: 32 x 32-bit register file, two read ports and one write port.
// x0 always reads as zero. A write in the same cycle as a read of the same
// register is passed straight to the read port (write-through), so the
// write-back stage never causes a stall.
module cvr32_regfile (
    input  logic        clk,
    input  logic [4:0]  ra1,     // read address 1 (rs1)
    input  logic [4:0]  ra2,     // read address 2 (rs2)
    output logic [31:0] rd1,
    output logic [31:0] rd2,
    input  logic        we,      // write enable from write-back
    input  logic [4:0]  wa,      // write address (rd)
    input  logic [31:0] wd       // write data
);

    logic [31:0] regs [1:31];

    always_ff @(posedge clk) begin
        if (we && wa != 5'd0)
            regs[wa] <= wd;
    end

    always @(*) begin
        if (ra1 == 5'd0)
            rd1 = 32'd0;
        else if (we && wa == ra1)
            rd1 = wd;
        else
            rd1 = regs[ra1];

        if (ra2 == 5'd0)
            rd2 = 32'd0;
        else if (we && wa == ra2)
            rd2 = wd;
        else
            rd2 = regs[ra2];
    end

endmodule

cvr32_decode.sv

// cvr32_decode: turns one RV32I instruction into the control signals the
// pipeline needs. Pure combinational logic, used in the decode (ID) stage.
module cvr32_decode (
    input  logic [31:0] instr,
    output logic [4:0]  rs1,
    output logic [4:0]  rs2,
    output logic [4:0]  rd,
    output logic [31:0] imm,        // sign-extended immediate for this format
    output logic [3:0]  alu_op,
    output logic [1:0]  a_sel,      // ALU operand A: 0 = rs1, 1 = PC, 2 = zero
    output logic        b_imm,      // ALU operand B: 1 = immediate, 0 = rs2
    output logic        reg_write,
    output logic        mem_read,
    output logic        mem_write,
    output logic [2:0]  funct3,     // load/store size or branch condition
    output logic        is_branch,
    output logic        is_jal,
    output logic        is_jalr,
    output logic        uses_rs1,   // used by the hazard logic
    output logic        uses_rs2
);

    localparam logic [6:0] OP_LUI    = 7'b0110111;
    localparam logic [6:0] OP_AUIPC  = 7'b0010111;
    localparam logic [6:0] OP_JAL    = 7'b1101111;
    localparam logic [6:0] OP_JALR   = 7'b1100111;
    localparam logic [6:0] OP_BRANCH = 7'b1100011;
    localparam logic [6:0] OP_LOAD   = 7'b0000011;
    localparam logic [6:0] OP_STORE  = 7'b0100011;
    localparam logic [6:0] OP_IMM    = 7'b0010011;
    localparam logic [6:0] OP_REG    = 7'b0110011;

    localparam logic [3:0] ALU_ADD  = 4'd0;
    localparam logic [3:0] ALU_SUB  = 4'd1;
    localparam logic [3:0] ALU_SLL  = 4'd2;
    localparam logic [3:0] ALU_SLT  = 4'd3;
    localparam logic [3:0] ALU_SLTU = 4'd4;
    localparam logic [3:0] ALU_XOR  = 4'd5;
    localparam logic [3:0] ALU_SRL  = 4'd6;
    localparam logic [3:0] ALU_SRA  = 4'd7;
    localparam logic [3:0] ALU_OR   = 4'd8;
    localparam logic [3:0] ALU_AND  = 4'd9;

    logic [6:0] opcode;
    logic [3:0] alu_f3;             // ALU operation chosen by funct3 (OP and OP-IMM)

    // the five immediate formats: the immediate's bits are spread over the
    // instruction differently in each, and every one is sign-extended
    // from instruction bit 31 to 32 bits
    logic [31:0] imm_i, imm_s, imm_b, imm_u, imm_j;
    assign imm_i = {{20{instr[31]}}, instr[31:20]};
    assign imm_s = {{20{instr[31]}}, instr[31:25], instr[11:7]};
    assign imm_b = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
    assign imm_u = {instr[31:12], 12'd0};
    assign imm_j = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};

    assign opcode = instr[6:0];
    assign rd     = instr[11:7];
    assign funct3 = instr[14:12];
    assign rs1    = instr[19:15];
    assign rs2    = instr[24:20];

    // funct3 to ALU operation; bit 30 picks SUB/SRA
    always @(*) begin
        case (funct3)
            3'b000:  alu_f3 = ALU_ADD;
            3'b001:  alu_f3 = ALU_SLL;
            3'b010:  alu_f3 = ALU_SLT;
            3'b011:  alu_f3 = ALU_SLTU;
            3'b100:  alu_f3 = ALU_XOR;
            3'b101:  alu_f3 = instr[30] ? ALU_SRA : ALU_SRL;
            3'b110:  alu_f3 = ALU_OR;
            default: alu_f3 = ALU_AND;
        endcase
    end

    always @(*) begin
        // defaults: an instruction that does nothing (FENCE and SYSTEM end up here)
        imm       = 32'd0;
        alu_op    = ALU_ADD;
        a_sel     = 2'd0;
        b_imm     = 1'b1;
        reg_write = 1'b0;
        mem_read  = 1'b0;
        mem_write = 1'b0;
        is_branch = 1'b0;
        is_jal    = 1'b0;
        is_jalr   = 1'b0;
        uses_rs1  = 1'b0;
        uses_rs2  = 1'b0;

        case (opcode)
            OP_LUI: begin                                    // rd = imm << 12
                imm       = imm_u;
                a_sel     = 2'd2;
                reg_write = 1'b1;
            end
            OP_AUIPC: begin                                  // rd = PC + (imm << 12)
                imm       = imm_u;
                a_sel     = 2'd1;
                reg_write = 1'b1;
            end
            OP_JAL: begin                                    // rd = PC + 4, jump to PC + imm
                imm       = imm_j;
                reg_write = 1'b1;
                is_jal    = 1'b1;
            end
            OP_JALR: begin                                   // rd = PC + 4, jump to rs1 + imm
                imm       = imm_i;
                reg_write = 1'b1;
                is_jalr   = 1'b1;
                uses_rs1  = 1'b1;
            end
            OP_BRANCH: begin                                 // compare rs1 and rs2, jump to PC + imm
                imm       = imm_b;
                is_branch = 1'b1;
                uses_rs1  = 1'b1;
                uses_rs2  = 1'b1;
            end
            OP_LOAD: begin                                   // rd = mem[rs1 + imm]
                imm       = imm_i;
                reg_write = 1'b1;
                mem_read  = 1'b1;
                uses_rs1  = 1'b1;
            end
            OP_STORE: begin                                  // mem[rs1 + imm] = rs2
                imm       = imm_s;
                mem_write = 1'b1;
                uses_rs1  = 1'b1;
                uses_rs2  = 1'b1;
            end
            OP_IMM: begin                                    // rd = rs1 op imm
                imm       = imm_i;
                alu_op    = alu_f3;                          // no SUBI: funct3 000 is always ADD
                reg_write = 1'b1;
                uses_rs1  = 1'b1;
            end
            OP_REG: begin                                    // rd = rs1 op rs2
                alu_op    = (funct3 == 3'b000 && instr[30]) ? ALU_SUB : alu_f3;
                b_imm     = 1'b0;
                reg_write = 1'b1;
                uses_rs1  = 1'b1;
                uses_rs2  = 1'b1;
            end
            default: ;
        endcase
    end

endmodule

cvr32_core.sv

// cvr32_core: a 5-stage in-order RV32I pipeline (IF, ID, EX, MEM, WB).
//
// - Branches and jumps resolve in EX. The core predicts "not taken", so a
//   taken branch or a jump flushes the two younger instructions.
// - With cfg_fwd_en = 1, results are forwarded from MEM and WB to EX, and only
//   a load followed by a dependent instruction stalls (one cycle).
//   With cfg_fwd_en = 0, a dependent instruction waits in ID until its source
//   reaches write-back.
// - Both memory ports have a ready signal; a slow data access freezes the pipe.
// - Every pipeline slot carries a "cause" tag. When WB sees an empty slot, the
//   tag says why it is empty, so cycles = instructions + sum of all bubbles.
module cvr32_core (
    input  logic        clk,
    input  logic        rst_n,
    input  logic        cfg_fwd_en,     // 1 = forwarding on

    // instruction port
    output logic [31:0] imem_addr,
    input  logic [31:0] imem_rdata,
    input  logic        imem_ready,

    // data port
    output logic [31:0] dmem_addr,
    output logic [31:0] dmem_wdata,
    output logic [3:0]  dmem_wstrb,
    output logic        dmem_we,
    output logic        dmem_re,
    input  logic [31:0] dmem_rdata,
    input  logic        dmem_ready
);

    // why a pipeline slot is empty
    localparam logic [2:0] B_START   = 3'd0;   // pipeline filling after reset
    localparam logic [2:0] B_FETCH   = 3'd1;   // instruction memory not ready
    localparam logic [2:0] B_LOADUSE = 3'd2;   // load followed by a dependent instruction
    localparam logic [2:0] B_RAW     = 3'd3;   // data dependency without forwarding
    localparam logic [2:0] B_FLUSH   = 3'd4;   // wrong-path instruction after a taken branch or jump
    localparam logic [2:0] B_DMEM    = 3'd5;   // data memory not ready

    // ------------------------------------------------------------------
    // Pipeline registers
    // ------------------------------------------------------------------
    logic [31:0] pc_f;

    // IF/ID
    logic        d_valid;
    logic [2:0]  d_cause;
    logic [31:0] d_pc, d_instr;

    // ID/EX
    logic        e_valid;
    logic [2:0]  e_cause;
    logic [31:0] e_pc, e_rv1, e_rv2, e_imm;
    logic [4:0]  e_rs1, e_rs2, e_rd;
    logic [3:0]  e_alu_op;
    logic [1:0]  e_a_sel;
    logic        e_b_imm, e_reg_write, e_mem_read, e_mem_write;
    logic        e_branch, e_jal, e_jalr;
    logic [2:0]  e_funct3;

    // EX/MEM
    logic        m_valid;
    logic [2:0]  m_cause;
    logic [31:0] m_result, m_store_data;
    logic [4:0]  m_rd;
    logic        m_reg_write, m_mem_read, m_mem_write;
    logic [2:0]  m_funct3;

    // MEM/WB
    logic        w_valid;
    logic [2:0]  w_cause;
    logic [31:0] w_value;
    logic [4:0]  w_rd;
    logic        w_reg_write;

    // ------------------------------------------------------------------
    // ID: decode and register read
    // ------------------------------------------------------------------
    logic [4:0]  d_rs1, d_rs2, d_rd;
    logic [31:0] d_imm, d_rv1, d_rv2;
    logic [3:0]  d_alu_op;
    logic [1:0]  d_a_sel;
    logic [2:0]  d_funct3;
    logic        d_b_imm, d_reg_write, d_mem_read, d_mem_write;
    logic        d_branch, d_jal, d_jalr, d_uses_rs1, d_uses_rs2;

    cvr32_decode u_decode (
        .instr     (d_instr),
        .rs1       (d_rs1),
        .rs2       (d_rs2),
        .rd        (d_rd),
        .imm       (d_imm),
        .alu_op    (d_alu_op),
        .a_sel     (d_a_sel),
        .b_imm     (d_b_imm),
        .reg_write (d_reg_write),
        .mem_read  (d_mem_read),
        .mem_write (d_mem_write),
        .funct3    (d_funct3),
        .is_branch (d_branch),
        .is_jal    (d_jal),
        .is_jalr   (d_jalr),
        .uses_rs1  (d_uses_rs1),
        .uses_rs2  (d_uses_rs2)
    );

    cvr32_regfile u_regfile (
        .clk (clk),
        .ra1 (d_rs1),
        .ra2 (d_rs2),
        .rd1 (d_rv1),
        .rd2 (d_rv2),
        .we  (w_valid && w_reg_write),
        .wa  (w_rd),
        .wd  (w_value)
    );

    // ------------------------------------------------------------------
    // Hazard detection
    // ------------------------------------------------------------------
    logic dep_e, dep_m;           // the ID instruction reads a register that EX / MEM will write
    logic load_use, raw_wait, id_stall, mem_stall, redirect;
    logic [2:0] stall_cause;

    assign dep_e = e_valid && e_reg_write && (e_rd != 5'd0) &&
                   ((d_uses_rs1 && d_rs1 == e_rd) || (d_uses_rs2 && d_rs2 == e_rd));
    assign dep_m = m_valid && m_reg_write && (m_rd != 5'd0) &&
                   ((d_uses_rs1 && d_rs1 == m_rd) || (d_uses_rs2 && d_rs2 == m_rd));

    // a load result is ready only after MEM, so even forwarding needs one bubble
    assign load_use = dep_e && e_mem_read;
    // without forwarding, wait until the producer has left EX and MEM
    assign raw_wait = !cfg_fwd_en && (dep_e || dep_m);

    assign id_stall    = d_valid && (load_use || raw_wait);
    assign stall_cause = load_use ? B_LOADUSE : B_RAW;

    // a data access that is not ready freezes the whole pipeline
    assign mem_stall = m_valid && (m_mem_read || m_mem_write) && !dmem_ready;

    // ------------------------------------------------------------------
    // EX: forwarding, ALU, branch resolution
    // ------------------------------------------------------------------
    logic [31:0] fwd_a, fwd_b, alu_a, alu_b, alu_y, ex_result, target;
    logic        taken;

    always @(*) begin
        fwd_a = e_rv1;
        fwd_b = e_rv2;
        if (cfg_fwd_en) begin
            if (m_valid && m_reg_write && m_rd != 5'd0 && m_rd == e_rs1)
                fwd_a = m_result;
            else if (w_valid && w_reg_write && w_rd != 5'd0 && w_rd == e_rs1)
                fwd_a = w_value;
            if (m_valid && m_reg_write && m_rd != 5'd0 && m_rd == e_rs2)
                fwd_b = m_result;
            else if (w_valid && w_reg_write && w_rd != 5'd0 && w_rd == e_rs2)
                fwd_b = w_value;
        end
    end

    assign alu_a = (e_a_sel == 2'd1) ? e_pc : (e_a_sel == 2'd2) ? 32'd0 : fwd_a;
    assign alu_b = e_b_imm ? e_imm : fwd_b;

    cvr32_alu u_alu (
        .op (e_alu_op),
        .a  (alu_a),
        .b  (alu_b),
        .y  (alu_y)
    );

    always @(*) begin
        case (e_funct3)
            3'b000:  taken = (fwd_a == fwd_b);                    // BEQ
            3'b001:  taken = (fwd_a != fwd_b);                    // BNE
            3'b100:  taken = ($signed(fwd_a) <  $signed(fwd_b));  // BLT
            3'b101:  taken = ($signed(fwd_a) >= $signed(fwd_b));  // BGE
            3'b110:  taken = (fwd_a <  fwd_b);                    // BLTU
            3'b111:  taken = (fwd_a >= fwd_b);                    // BGEU
            default: taken = 1'b0;
        endcase
    end

    assign target    = e_jalr ? ((fwd_a + e_imm) & ~32'd1) : (e_pc + e_imm);
    assign ex_result = (e_jal || e_jalr) ? (e_pc + 32'd4) : alu_y;
    assign redirect  = e_valid && !mem_stall && (e_jal || e_jalr || (e_branch && taken));

    // ------------------------------------------------------------------
    // MEM: data port and load alignment
    // ------------------------------------------------------------------
    logic [31:0] load_shifted, load_value, m_value;

    assign dmem_addr = m_result;
    assign dmem_re   = m_valid && m_mem_read;
    assign dmem_we   = m_valid && m_mem_write;

    always @(*) begin
        case (m_funct3[1:0])
            2'b00: begin                                          // SB
                dmem_wdata = {4{m_store_data[7:0]}};
                dmem_wstrb = 4'b0001 << m_result[1:0];
            end
            2'b01: begin                                          // SH
                dmem_wdata = {2{m_store_data[15:0]}};
                dmem_wstrb = m_result[1] ? 4'b1100 : 4'b0011;
            end
            default: begin                                        // SW
                dmem_wdata = m_store_data;
                dmem_wstrb = 4'b1111;
            end
        endcase
    end

    assign load_shifted = dmem_rdata >> {m_result[1:0], 3'b000};

    always @(*) begin
        case (m_funct3)
            3'b000:  load_value = {{24{load_shifted[7]}},  load_shifted[7:0]};   // LB
            3'b001:  load_value = {{16{load_shifted[15]}}, load_shifted[15:0]};  // LH
            3'b100:  load_value = {24'd0, load_shifted[7:0]};                    // LBU
            3'b101:  load_value = {16'd0, load_shifted[15:0]};                   // LHU
            default: load_value = dmem_rdata;                                    // LW
        endcase
    end

    assign m_value = m_mem_read ? load_value : m_result;

    // ------------------------------------------------------------------
    // Pipeline register updates
    // ------------------------------------------------------------------
    assign imem_addr = pc_f;

    // IF: program counter
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            pc_f <= 32'd0;
        else if (mem_stall)
            pc_f <= pc_f;
        else if (redirect)
            pc_f <= target;
        else if (id_stall || !imem_ready)
            pc_f <= pc_f;
        else
            pc_f <= pc_f + 32'd4;
    end

    // IF/ID
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            d_valid <= 1'b0;
            d_cause <= B_START;
            d_pc    <= 32'd0;
            d_instr <= 32'h0000_0013;                             // NOP (addi x0, x0, 0)
        end else if (mem_stall || (id_stall && !redirect)) begin
            // hold
        end else if (redirect) begin
            d_valid <= 1'b0;
            d_cause <= B_FLUSH;
        end else if (!imem_ready) begin
            d_valid <= 1'b0;
            d_cause <= B_FETCH;
        end else begin
            d_valid <= 1'b1;
            d_pc    <= pc_f;
            d_instr <= imem_rdata;
        end
    end

    // ID/EX: valid bit and bubble cause (reset)
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            e_valid <= 1'b0;
            e_cause <= B_START;
        end else if (mem_stall) begin
            // hold
        end else if (redirect) begin
            e_valid <= 1'b0;
            e_cause <= B_FLUSH;
        end else if (id_stall) begin
            e_valid <= 1'b0;
            e_cause <= stall_cause;
        end else begin
            e_valid <= d_valid;
            e_cause <= d_cause;
        end
    end

    // ID/EX: instruction data (no reset needed, e_valid qualifies it)
    always_ff @(posedge clk) begin
        if (mem_stall) begin
            // hold the instruction, but keep its operands current: a value it
            // gets by forwarding from WB disappears while the pipe is frozen
            e_rv1 <= fwd_a;
            e_rv2 <= fwd_b;
        end else if (!redirect && !id_stall) begin
            e_pc        <= d_pc;
            e_rv1       <= d_rv1;
            e_rv2       <= d_rv2;
            e_imm       <= d_imm;
            e_rs1       <= d_rs1;
            e_rs2       <= d_rs2;
            e_rd        <= d_rd;
            e_alu_op    <= d_alu_op;
            e_a_sel     <= d_a_sel;
            e_b_imm     <= d_b_imm;
            e_reg_write <= d_reg_write;
            e_mem_read  <= d_mem_read;
            e_mem_write <= d_mem_write;
            e_branch    <= d_branch;
            e_jal       <= d_jal;
            e_jalr      <= d_jalr;
            e_funct3    <= d_funct3;
        end
    end

    // EX/MEM
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            m_valid <= 1'b0;
            m_cause <= B_START;
        end else if (!mem_stall) begin
            m_valid      <= e_valid;
            m_cause      <= e_cause;
            m_result     <= ex_result;
            m_store_data <= fwd_b;
            m_rd         <= e_rd;
            m_reg_write  <= e_reg_write;
            m_mem_read   <= e_mem_read;
            m_mem_write  <= e_mem_write;
            m_funct3     <= e_funct3;
        end
    end

    // MEM/WB
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            w_valid <= 1'b0;
            w_cause <= B_START;
        end else if (mem_stall) begin
            w_valid <= 1'b0;
            w_cause <= B_DMEM;
        end else begin
            w_valid     <= m_valid;
            w_cause     <= m_cause;
            w_value     <= m_value;
            w_rd        <= m_rd;
            w_reg_write <= m_reg_write;
        end
    end

    // ------------------------------------------------------------------
    // Performance counters (counted where instructions retire, in WB)
    // ------------------------------------------------------------------
    logic [63:0] perf_cycles, perf_instret;
    logic [31:0] perf_bubble [0:5];
    logic [31:0] perf_branches, perf_taken, perf_jumps, perf_loads, perf_stores;

    // cycles and retired instructions: the two numbers behind CPI
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            perf_cycles  <= '0;
            perf_instret <= '0;
        end else begin
            perf_cycles <= perf_cycles + 1'b1;
            if (w_valid)
                perf_instret <= perf_instret + 1'b1;
        end
    end

    // empty pipeline slots, by the reason they are empty
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            for (int i = 0; i < 6; i++)
                perf_bubble[i] <= 32'd0;
        end else begin
            if (!w_valid)
                perf_bubble[w_cause] <= perf_bubble[w_cause] + 32'd1;
        end
    end

    // instruction mix, counted when an instruction leaves EX
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            perf_branches <= 32'd0;
            perf_taken    <= 32'd0;
            perf_jumps    <= 32'd0;
            perf_loads    <= 32'd0;
            perf_stores   <= 32'd0;
        end else if (e_valid && !mem_stall) begin
            if (e_branch)
                perf_branches <= perf_branches + 32'd1;
            if (e_branch && taken)
                perf_taken <= perf_taken + 32'd1;
            if (e_jal || e_jalr)
                perf_jumps <= perf_jumps + 32'd1;
            if (e_mem_read)
                perf_loads <= perf_loads + 32'd1;
            if (e_mem_write)
                perf_stores <= perf_stores + 32'd1;
        end
    end

endmodule

cvsoc_cpu_subsys.sv

// cvsoc_cpu_subsys: the CPU subsystem of cvsoc.
//
// - cvr32 core
// - 64 KB tightly coupled memory (TCM) at 0x0000_0000: code, data and stack,
//   one-cycle access from both the instruction and the data port
// - every other data address goes out on an AXI4-Lite master port
//
// The AXI4-Lite master handles one transaction at a time: the core's memory
// stage waits (dmem_ready = 0) until the response comes back.
module cvsoc_cpu_subsys (
    input  logic        clk,
    input  logic        rst_n,

    // AXI4-Lite master port (to the interconnect)
    output logic [31:0] m_awaddr,
    output logic        m_awvalid,
    input  logic        m_awready,
    output logic [31:0] m_wdata,
    output logic [3:0]  m_wstrb,
    output logic        m_wvalid,
    input  logic        m_wready,
    input  logic [1:0]  m_bresp,
    input  logic        m_bvalid,
    output logic        m_bready,
    output logic [31:0] m_araddr,
    output logic        m_arvalid,
    input  logic        m_arready,
    input  logic [31:0] m_rdata,
    input  logic [1:0]  m_rresp,
    input  logic        m_rvalid,
    output logic        m_rready
);

    // ------------------------------------------------------------------
    // Core
    // ------------------------------------------------------------------
    logic [31:0] imem_addr, imem_rdata;
    logic [31:0] dmem_addr, dmem_wdata, dmem_rdata;
    logic [3:0]  dmem_wstrb;
    logic        dmem_we, dmem_re, dmem_ready;

    cvr32_core u_core (
        .clk        (clk),
        .rst_n      (rst_n),
        .cfg_fwd_en (1'b1),
        .imem_addr  (imem_addr),
        .imem_rdata (imem_rdata),
        .imem_ready (1'b1),
        .dmem_addr  (dmem_addr),
        .dmem_wdata (dmem_wdata),
        .dmem_wstrb (dmem_wstrb),
        .dmem_we    (dmem_we),
        .dmem_re    (dmem_re),
        .dmem_rdata (dmem_rdata),
        .dmem_ready (dmem_ready)
    );

    // ------------------------------------------------------------------
    // Local address decode: TCM or bus
    // ------------------------------------------------------------------
    logic d_tcm, d_bus;
    assign d_tcm = (dmem_addr[31:16] == 16'h0000);
    assign d_bus = (dmem_we || dmem_re) && !d_tcm;

    // ------------------------------------------------------------------
    // TCM: 16K x 32-bit words, instruction port + data port
    // ------------------------------------------------------------------
    logic [31:0] tcm [0:16383];

    assign imem_rdata = tcm[imem_addr[15:2]];

    always_ff @(posedge clk) begin
        if (dmem_we && d_tcm) begin
            for (int b = 0; b < 4; b++)
                if (dmem_wstrb[b])
                    tcm[dmem_addr[15:2]][8*b +: 8] <= dmem_wdata[8*b +: 8];
        end
    end

    // ------------------------------------------------------------------
    // AXI4-Lite master: one transaction at a time
    // ------------------------------------------------------------------
    localparam logic [1:0] S_IDLE = 2'd0;
    localparam logic [1:0] S_WRITE = 2'd1;
    localparam logic [1:0] S_READ = 2'd2;
    localparam logic [1:0] S_DONE = 2'd3;

    logic [1:0]  state;
    logic        aw_done, w_done;
    logic [31:0] bus_rdata;
    logic        bus_error;                // last response was SLVERR or DECERR

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            state     <= S_IDLE;
            aw_done   <= 1'b0;
            w_done    <= 1'b0;
            bus_rdata <= 32'd0;
            bus_error <= 1'b0;
        end else begin
            case (state)
                S_IDLE: begin
                    if (d_bus) begin
                        aw_done <= 1'b0;
                        w_done  <= 1'b0;
                        state   <= dmem_we ? S_WRITE : S_READ;
                    end
                end
                S_WRITE: begin
                    if (m_awvalid && m_awready)
                        aw_done <= 1'b1;
                    if (m_wvalid && m_wready)
                        w_done <= 1'b1;
                    if (m_bvalid) begin
                        bus_error <= (m_bresp != 2'b00);
                        state     <= S_DONE;
                    end
                end
                S_READ: begin
                    if (m_rvalid) begin
                        bus_rdata <= m_rdata;
                        bus_error <= (m_rresp != 2'b00);
                        state     <= S_DONE;
                    end
                end
                default: state <= S_IDLE;           // S_DONE: the core takes the result this cycle
            endcase
        end
    end

    assign m_awaddr  = dmem_addr;
    assign m_awvalid = (state == S_WRITE) && !aw_done;
    assign m_wdata   = dmem_wdata;
    assign m_wstrb   = dmem_wstrb;
    assign m_wvalid  = (state == S_WRITE) && !w_done;
    assign m_bready  = (state == S_WRITE);

    // the read address is offered in the cycle after the request is seen
    logic ar_done;
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            ar_done <= 1'b0;
        else if (state == S_IDLE)
            ar_done <= 1'b0;
        else if (m_arvalid && m_arready)
            ar_done <= 1'b1;
    end

    assign m_araddr  = dmem_addr;
    assign m_arvalid = (state == S_READ) && !ar_done;
    assign m_rready  = (state == S_READ);

    // ------------------------------------------------------------------
    // Data back to the core
    // ------------------------------------------------------------------
    assign dmem_ready = !d_bus || (state == S_DONE);
    assign dmem_rdata = d_tcm ? tcm[dmem_addr[15:2]] : bus_rdata;

endmodule

cvsoc_axil_xbar.sv

// cvsoc_axil_xbar: AXI4-Lite interconnect, 1 master to N slaves.
//
// Each slave owns the address window [BASE, BASE + SIZE). The interconnect
// routes a transaction to the slave whose window holds the address. An
// address that no slave owns gets a DECERR response from the interconnect
// itself, so the master never hangs.
//
// Slave signals are packed side by side: slave i uses bits [32*i +: 32] of a
// 32-bit field and bit [i] of a 1-bit field.
module cvsoc_axil_xbar #(
    parameter int          N    = 2,
    parameter logic [63:0] BASE = {32'h4000_0000, 32'h2000_0000},  // slave 1, slave 0
    parameter logic [63:0] SIZE = {32'h0001_0000, 32'h0000_4000}
) (
    input  logic            clk,
    input  logic            rst_n,

    // from the master
    input  logic [31:0]     s_awaddr,
    input  logic            s_awvalid,
    output logic            s_awready,
    input  logic [31:0]     s_wdata,
    input  logic [3:0]      s_wstrb,
    input  logic            s_wvalid,
    output logic            s_wready,
    output logic [1:0]      s_bresp,
    output logic            s_bvalid,
    input  logic            s_bready,
    input  logic [31:0]     s_araddr,
    input  logic            s_arvalid,
    output logic            s_arready,
    output logic [31:0]     s_rdata,
    output logic [1:0]      s_rresp,
    output logic            s_rvalid,
    input  logic            s_rready,

    // to the slaves
    output logic [32*N-1:0] m_awaddr,
    output logic [N-1:0]    m_awvalid,
    input  logic [N-1:0]    m_awready,
    output logic [32*N-1:0] m_wdata,
    output logic [4*N-1:0]  m_wstrb,
    output logic [N-1:0]    m_wvalid,
    input  logic [N-1:0]    m_wready,
    input  logic [2*N-1:0]  m_bresp,
    input  logic [N-1:0]    m_bvalid,
    output logic [N-1:0]    m_bready,
    output logic [32*N-1:0] m_araddr,
    output logic [N-1:0]    m_arvalid,
    input  logic [N-1:0]    m_arready,
    input  logic [32*N-1:0] m_rdata,
    input  logic [2*N-1:0]  m_rresp,
    input  logic [N-1:0]    m_rvalid,
    output logic [N-1:0]    m_rready
);

    // ------------------------------------------------------------------
    // Address decode: one-hot slave select, all zero = no slave
    // ------------------------------------------------------------------
    function automatic logic [N-1:0] decode(input logic [31:0] addr);
        logic [N-1:0] sel;
        sel = '0;
        for (int i = 0; i < N; i++)
            if (addr >= BASE[32*i +: 32] && addr - BASE[32*i +: 32] < SIZE[32*i +: 32])
                sel[i] = 1'b1;
        decode = sel;
    endfunction

    logic [N-1:0] aw_sel, ar_sel;
    assign aw_sel = decode(s_awaddr);
    assign ar_sel = decode(s_araddr);

    // ------------------------------------------------------------------
    // Write path: address and data fan out, the response comes back from
    // the selected slave. wr_sel remembers the target until B is accepted.
    // ------------------------------------------------------------------
    logic [N-1:0] wr_sel;
    logic         wr_busy, wr_err, wr_err_bvalid;

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            wr_busy       <= 1'b0;
            wr_sel        <= '0;
            wr_err        <= 1'b0;
            wr_err_bvalid <= 1'b0;
        end else begin
            if (!wr_busy && s_awvalid) begin
                wr_busy <= 1'b1;
                wr_sel  <= aw_sel;
                wr_err  <= (aw_sel == '0);
            end
            // a decode error is answered once both address and data have arrived
            if (wr_busy && wr_err && s_wvalid && !wr_err_bvalid)
                wr_err_bvalid <= 1'b1;
            if (s_bvalid && s_bready) begin
                wr_busy       <= 1'b0;
                wr_err        <= 1'b0;
                wr_err_bvalid <= 1'b0;
            end
        end
    end

    logic [N-1:0] wr_route;           // selected slave, valid from the first cycle
    assign wr_route = wr_busy ? wr_sel : aw_sel;

    always @(*) begin
        for (int i = 0; i < N; i++) begin
            m_awaddr[32*i +: 32] = s_awaddr;
            m_wdata[32*i +: 32]  = s_wdata;
            m_wstrb[4*i +: 4]    = s_wstrb;
            m_awvalid[i]         = s_awvalid && wr_route[i];
            m_wvalid[i]          = s_wvalid && wr_route[i];
            m_bready[i]          = s_bready && wr_sel[i] && wr_busy;
        end
        s_awready = 1'b0;
        s_wready  = 1'b0;
        s_bvalid  = 1'b0;
        s_bresp   = 2'b00;
        for (int i = 0; i < N; i++) begin
            if (wr_route[i]) begin
                s_awready = m_awready[i];
                s_wready  = m_wready[i];
            end
            if (wr_busy && wr_sel[i]) begin
                s_bvalid = m_bvalid[i];
                s_bresp  = m_bresp[2*i +: 2];
            end
        end
        if (wr_route == '0) begin           // no slave: accept and answer DECERR
            s_awready = s_awvalid;
            s_wready  = s_wvalid && wr_busy;
        end
        if (wr_err_bvalid) begin
            s_bvalid = 1'b1;
            s_bresp  = 2'b11;
        end
    end

    // ------------------------------------------------------------------
    // Read path: same idea
    // ------------------------------------------------------------------
    logic [N-1:0] rd_sel;
    logic         rd_busy, rd_err;

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            rd_busy <= 1'b0;
            rd_sel  <= '0;
            rd_err  <= 1'b0;
        end else begin
            if (!rd_busy && s_arvalid) begin
                rd_busy <= 1'b1;
                rd_sel  <= ar_sel;
                rd_err  <= (ar_sel == '0);
            end
            if (s_rvalid && s_rready) begin
                rd_busy <= 1'b0;
                rd_err  <= 1'b0;
            end
        end
    end

    logic [N-1:0] rd_route;
    assign rd_route = rd_busy ? rd_sel : ar_sel;

    always @(*) begin
        for (int i = 0; i < N; i++) begin
            m_araddr[32*i +: 32] = s_araddr;
            m_arvalid[i]         = s_arvalid && rd_route[i];
            m_rready[i]          = s_rready && rd_sel[i] && rd_busy;
        end
        s_arready = 1'b0;
        s_rvalid  = 1'b0;
        s_rdata   = 32'd0;
        s_rresp   = 2'b00;
        for (int i = 0; i < N; i++) begin
            if (rd_route[i])
                s_arready = m_arready[i];
            if (rd_busy && rd_sel[i]) begin
                s_rvalid = m_rvalid[i];
                s_rdata  = m_rdata[32*i +: 32];
                s_rresp  = m_rresp[2*i +: 2];
            end
        end
        if (rd_route == '0)
            s_arready = s_arvalid;
        if (rd_busy && rd_err) begin
            s_rvalid = 1'b1;
            s_rresp  = 2'b11;
        end
    end

endmodule

cvsoc_axil_sram.sv

// cvsoc_axil_sram: system SRAM behind an AXI4-Lite slave port.
// A write is accepted when address and data are both present; the response
// follows one cycle later. A read returns data one cycle after the address.
module cvsoc_axil_sram #(
    parameter int WORDS = 4096                     // 16 KB
) (
    input  logic        clk,
    input  logic        rst_n,
    input  logic [31:0] s_awaddr,
    input  logic        s_awvalid,
    output logic        s_awready,
    input  logic [31:0] s_wdata,
    input  logic [3:0]  s_wstrb,
    input  logic        s_wvalid,
    output logic        s_wready,
    output logic [1:0]  s_bresp,
    output logic        s_bvalid,
    input  logic        s_bready,
    input  logic [31:0] s_araddr,
    input  logic        s_arvalid,
    output logic        s_arready,
    output logic [31:0] s_rdata,
    output logic [1:0]  s_rresp,
    output logic        s_rvalid,
    input  logic        s_rready
);

    localparam int AW = $clog2(WORDS);

    logic [31:0] mem [0:WORDS-1];

    // write: take address and data together, then answer
    assign s_awready = s_awvalid && s_wvalid && !s_bvalid;
    assign s_wready  = s_awready;
    assign s_bresp   = 2'b00;

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            s_bvalid <= 1'b0;
        else if (s_awready)
            s_bvalid <= 1'b1;
        else if (s_bready)
            s_bvalid <= 1'b0;
    end

    always_ff @(posedge clk) begin
        if (s_awready)
            for (int b = 0; b < 4; b++)
                if (s_wstrb[b])
                    mem[s_awaddr[AW+1:2]][8*b +: 8] <= s_wdata[8*b +: 8];
    end

    // read
    assign s_arready = s_arvalid && !s_rvalid;
    assign s_rresp   = 2'b00;

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            s_rvalid <= 1'b0;
        else if (s_arready)
            s_rvalid <= 1'b1;
        else if (s_rready)
            s_rvalid <= 1'b0;
    end

    always_ff @(posedge clk) begin
        if (s_arready)
            s_rdata <= mem[s_araddr[AW+1:2]];
    end

endmodule

cvsoc_axil2apb.sv

// cvsoc_axil2apb: AXI4-Lite slave to APB bridge for the peripheral block.
//
// Each AXI4-Lite transaction becomes one APB transfer: a SETUP cycle (PSEL=1,
// PENABLE=0) and then ACCESS cycles (PENABLE=1) until the peripheral raises
// PREADY. Up to 16 peripherals sit behind the bridge, each with a 4 KB window
// chosen by address bits [15:12].
module cvsoc_axil2apb #(
    parameter int NP = 4                             // number of APB peripherals
) (
    input  logic          clk,
    input  logic          rst_n,

    // AXI4-Lite slave
    input  logic [31:0]   s_awaddr,
    input  logic          s_awvalid,
    output logic          s_awready,
    input  logic [31:0]   s_wdata,
    input  logic [3:0]    s_wstrb,
    input  logic          s_wvalid,
    output logic          s_wready,
    output logic [1:0]    s_bresp,
    output logic          s_bvalid,
    input  logic          s_bready,
    input  logic [31:0]   s_araddr,
    input  logic          s_arvalid,
    output logic          s_arready,
    output logic [31:0]   s_rdata,
    output logic [1:0]    s_rresp,
    output logic          s_rvalid,
    input  logic          s_rready,

    // APB master (shared signals, one PSEL per peripheral)
    input  logic [4*NP-1:0]  slot,                   // address bits [15:12] of each peripheral
    output logic [NP-1:0]    psel,
    output logic             penable,
    output logic             pwrite,
    output logic [11:0]      paddr,
    output logic [31:0]      pwdata,
    output logic [3:0]       pstrb,
    input  logic [32*NP-1:0] prdata,
    input  logic [NP-1:0]    pready,
    input  logic [NP-1:0]    pslverr
);

    localparam logic [1:0] S_IDLE   = 2'd0;
    localparam logic [1:0] S_SETUP  = 2'd1;
    localparam logic [1:0] S_ACCESS = 2'd2;
    localparam logic [1:0] S_RESP   = 2'd3;

    logic [1:0]    state;
    logic          is_write, no_target;
    logic [31:0]   addr, wdata, rdata;
    logic [3:0]    strb;
    logic [NP-1:0] sel;
    logic          err;

    // which peripheral owns an address
    function automatic logic [NP-1:0] find(input logic [31:0] a);
        logic [NP-1:0] f;
        f = '0;
        for (int i = 0; i < NP; i++)
            if (a[15:12] == slot[4*i +: 4])
                f[i] = 1'b1;
        find = f;
    endfunction

    // accept a write (address + data) or a read when idle; writes go first
    assign s_awready = (state == S_IDLE) && s_awvalid && s_wvalid;
    assign s_wready  = s_awready;
    assign s_arready = (state == S_IDLE) && s_arvalid && !(s_awvalid && s_wvalid);

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            state     <= S_IDLE;
            is_write  <= 1'b0;
            no_target <= 1'b0;
            sel       <= '0;
            err       <= 1'b0;
            addr      <= 32'd0;
            wdata     <= 32'd0;
            rdata     <= 32'd0;
            strb      <= 4'd0;
        end else begin
            case (state)
                S_IDLE: begin
                    if (s_awready) begin
                        is_write  <= 1'b1;
                        addr      <= s_awaddr;
                        wdata     <= s_wdata;
                        strb      <= s_wstrb;
                        sel       <= find(s_awaddr);
                        no_target <= (find(s_awaddr) == '0);
                        state     <= S_SETUP;
                    end else if (s_arready) begin
                        is_write  <= 1'b0;
                        addr      <= s_araddr;
                        sel       <= find(s_araddr);
                        no_target <= (find(s_araddr) == '0);
                        state     <= S_SETUP;
                    end
                end
                S_SETUP: begin
                    if (no_target) begin                     // nothing there: slave error
                        err   <= 1'b1;
                        rdata <= 32'd0;
                        state <= S_RESP;
                    end else begin
                        state <= S_ACCESS;
                    end
                end
                S_ACCESS: begin
                    for (int i = 0; i < NP; i++)
                        if (sel[i] && pready[i]) begin
                            rdata <= prdata[32*i +: 32];
                            err   <= pslverr[i];
                            state <= S_RESP;
                        end
                end
                default: begin                               // S_RESP
                    if ((is_write && s_bready) || (!is_write && s_rready)) begin
                        err   <= 1'b0;
                        state <= S_IDLE;
                    end
                end
            endcase
        end
    end

    assign psel    = (state == S_SETUP || state == S_ACCESS) ? sel : '0;
    assign penable = (state == S_ACCESS);
    assign pwrite  = is_write;
    assign paddr   = addr[11:0];
    assign pwdata  = wdata;
    assign pstrb   = strb;

    assign s_bvalid = (state == S_RESP) && is_write;
    assign s_bresp  = err ? 2'b10 : 2'b00;               // SLVERR
    assign s_rvalid = (state == S_RESP) && !is_write;
    assign s_rdata  = rdata;
    assign s_rresp  = err ? 2'b10 : 2'b00;

endmodule

cvsoc_periph.sv

// cvsoc peripherals on APB: UART transmitter, timer, GPIO and simulation control.
// Every peripheral answers in the first ACCESS cycle (PREADY = 1).

// ----------------------------------------------------------------------
// UART transmitter: 8 data bits, no parity, 1 stop bit, 8-byte FIFO.
//   0x000 TXDATA  write: queue one byte
//   0x004 STATUS  bit 0 = FIFO full, bit 1 = busy (a byte is queued or being sent)
//   0x008 DIV     clock cycles per bit (reset 16)
// ----------------------------------------------------------------------
module cvsoc_uart (
    input  logic        clk,
    input  logic        rst_n,
    input  logic        psel,
    input  logic        penable,
    input  logic        pwrite,
    input  logic [11:0] paddr,
    input  logic [31:0] pwdata,
    output logic [31:0] prdata,
    output logic        pready,
    output logic        pslverr,
    output logic        tx                          // serial line, idle high
);

    logic [7:0]  fifo [0:7];
    logic [2:0]  wptr, rptr;
    logic [3:0]  count;
    logic [15:0] div;
    logic [15:0] baud_cnt;
    logic [3:0]  bit_idx;                           // 0 = start, 1..8 = data, 9 = stop
    logic [7:0]  shift;
    logic        busy;
    logic        wr, pop;

    assign pready  = 1'b1;
    assign pslverr = 1'b0;
    assign wr      = psel && penable && pwrite;

    always @(*) begin
        case (paddr)
            12'h004: prdata = {30'd0, busy || (count != 4'd0), count == 4'd8};
            12'h008: prdata = {16'd0, div};
            default: prdata = 32'd0;
        endcase
    end

    assign pop = !busy && (count != 4'd0);

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            wptr     <= 3'd0;
            rptr     <= 3'd0;
            count    <= 4'd0;
            div      <= 16'd16;
            busy     <= 1'b0;
            baud_cnt <= 16'd0;
            bit_idx  <= 4'd0;
            shift    <= 8'd0;
            tx       <= 1'b1;
        end else begin
            // register writes
            if (wr && paddr == 12'h000 && count != 4'd8) begin
                fifo[wptr] <= pwdata[7:0];
                wptr       <= wptr + 3'd1;
            end
            if (wr && paddr == 12'h008)
                div <= pwdata[15:0];
            count <= count + ((wr && paddr == 12'h000 && count != 4'd8) ? 4'd1 : 4'd0)
                           - (pop ? 4'd1 : 4'd0);

            // transmitter
            if (pop) begin
                shift    <= fifo[rptr];
                rptr     <= rptr + 3'd1;
                busy     <= 1'b1;
                bit_idx  <= 4'd0;
                baud_cnt <= 16'd0;
                tx       <= 1'b0;                   // start bit
            end else if (busy) begin
                if (baud_cnt == div - 16'd1) begin
                    baud_cnt <= 16'd0;
                    bit_idx  <= bit_idx + 4'd1;
                    if (bit_idx < 4'd8) begin
                        tx    <= shift[0];          // LSB first
                        shift <= shift >> 1;
                    end else if (bit_idx == 4'd8) begin
                        tx <= 1'b1;                 // stop bit
                    end else begin
                        busy <= 1'b0;
                    end
                end else begin
                    baud_cnt <= baud_cnt + 16'd1;
                end
            end
        end
    end

endmodule

// ----------------------------------------------------------------------
// Timer: a 64-bit counter that increments every clock, and a compare value.
//   0x000 MTIME_LO   0x004 MTIME_HI   (read only)
//   0x008 CMP_LO     0x00C CMP_HI     irq = 1 while MTIME >= CMP
// ----------------------------------------------------------------------
module cvsoc_timer (
    input  logic        clk,
    input  logic        rst_n,
    input  logic        psel,
    input  logic        penable,
    input  logic        pwrite,
    input  logic [11:0] paddr,
    input  logic [31:0] pwdata,
    output logic [31:0] prdata,
    output logic        pready,
    output logic        pslverr,
    output logic        irq
);

    logic [63:0] mtime, cmp;

    assign pready  = 1'b1;
    assign pslverr = 1'b0;
    assign irq     = (mtime >= cmp);

    always @(*) begin
        case (paddr)
            12'h000: prdata = mtime[31:0];
            12'h004: prdata = mtime[63:32];
            12'h008: prdata = cmp[31:0];
            12'h00C: prdata = cmp[63:32];
            default: prdata = 32'd0;
        endcase
    end

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            mtime <= 64'd0;
            cmp   <= 64'hFFFF_FFFF_FFFF_FFFF;
        end else begin
            mtime <= mtime + 64'd1;
            if (psel && penable && pwrite && paddr == 12'h008)
                cmp[31:0] <= pwdata;
            if (psel && penable && pwrite && paddr == 12'h00C)
                cmp[63:32] <= pwdata;
        end
    end

endmodule

// ----------------------------------------------------------------------
// GPIO: 32 outputs and 32 inputs.
//   0x000 OUT (read/write)   0x004 IN (read only)
// ----------------------------------------------------------------------
module cvsoc_gpio (
    input  logic        clk,
    input  logic        rst_n,
    input  logic        psel,
    input  logic        penable,
    input  logic        pwrite,
    input  logic [11:0] paddr,
    input  logic [31:0] pwdata,
    output logic [31:0] prdata,
    output logic        pready,
    output logic        pslverr,
    output logic [31:0] gpio_out,
    input  logic [31:0] gpio_in
);

    assign pready  = 1'b1;
    assign pslverr = 1'b0;
    assign prdata  = (paddr == 12'h004) ? gpio_in : gpio_out;

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            gpio_out <= 32'd0;
        else if (psel && penable && pwrite && paddr == 12'h000)
            gpio_out <= pwdata;
    end

endmodule

// ----------------------------------------------------------------------
// Simulation control (simulation only, not real hardware): the program
// writes its result here to end the test.
//   0x000 EXIT  write: done = 1, code = written value
// ----------------------------------------------------------------------
module cvsoc_simctrl (
    input  logic        clk,
    input  logic        rst_n,
    input  logic        psel,
    input  logic        penable,
    input  logic        pwrite,
    input  logic [11:0] paddr,
    input  logic [31:0] pwdata,
    output logic [31:0] prdata,
    output logic        pready,
    output logic        pslverr,
    output logic        done,
    output logic [31:0] code
);

    assign pready  = 1'b1;
    assign pslverr = 1'b0;
    assign prdata  = code;

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            done <= 1'b0;
            code <= 32'd0;
        end else if (psel && penable && pwrite && paddr == 12'h000 && !done) begin
            done <= 1'b1;
            code <= pwdata;
        end
    end

endmodule

cvsoc_top.sv

// cvsoc_top: the cvsoc reference SoC, version 0.
//
// Memory map
//   0x0000_0000 - 0x0000_FFFF  TCM, 64 KB (inside the CPU subsystem)
//   0x2000_0000 - 0x2000_3FFF  system SRAM, 16 KB      (AXI4-Lite slave 0)
//   0x4000_0000 - 0x4000_FFFF  peripherals on APB      (AXI4-Lite slave 1)
//       0x4000_0000  UART
//       0x4000_1000  timer
//       0x4000_2000  GPIO
//       0x4000_F000  simulation control (simulation only)
//   anything else              DECERR from the interconnect
module cvsoc_top (
    input  logic        clk,
    input  logic        rst_n,
    output logic        uart_tx,
    output logic [31:0] gpio_out,
    input  logic [31:0] gpio_in,
    output logic        timer_irq,
    output logic        sim_done,
    output logic [31:0] sim_code
);

    // ------------------------------------------------------------------
    // CPU subsystem -> interconnect
    // ------------------------------------------------------------------
    logic [31:0] c_awaddr, c_wdata, c_araddr, c_rdata;
    logic [3:0]  c_wstrb;
    logic [1:0]  c_bresp, c_rresp;
    logic        c_awvalid, c_awready, c_wvalid, c_wready, c_bvalid, c_bready;
    logic        c_arvalid, c_arready, c_rvalid, c_rready;

    cvsoc_cpu_subsys u_cpu (
        .clk       (clk),
        .rst_n     (rst_n),
        .m_awaddr  (c_awaddr),
        .m_awvalid (c_awvalid),
        .m_awready (c_awready),
        .m_wdata   (c_wdata),
        .m_wstrb   (c_wstrb),
        .m_wvalid  (c_wvalid),
        .m_wready  (c_wready),
        .m_bresp   (c_bresp),
        .m_bvalid  (c_bvalid),
        .m_bready  (c_bready),
        .m_araddr  (c_araddr),
        .m_arvalid (c_arvalid),
        .m_arready (c_arready),
        .m_rdata   (c_rdata),
        .m_rresp   (c_rresp),
        .m_rvalid  (c_rvalid),
        .m_rready  (c_rready)
    );

    // ------------------------------------------------------------------
    // Interconnect: slave 0 = SRAM, slave 1 = APB bridge
    // ------------------------------------------------------------------
    localparam int NS = 2;

    logic [32*NS-1:0] x_awaddr, x_wdata, x_araddr, x_rdata;
    logic [4*NS-1:0]  x_wstrb;
    logic [2*NS-1:0]  x_bresp, x_rresp;
    logic [NS-1:0]    x_awvalid, x_awready, x_wvalid, x_wready, x_bvalid, x_bready;
    logic [NS-1:0]    x_arvalid, x_arready, x_rvalid, x_rready;

    cvsoc_axil_xbar #(
        .N    (NS),
        .BASE ({32'h4000_0000, 32'h2000_0000}),
        .SIZE ({32'h0001_0000, 32'h0000_4000})
    ) u_xbar (
        .clk       (clk),
        .rst_n     (rst_n),
        .s_awaddr  (c_awaddr),
        .s_awvalid (c_awvalid),
        .s_awready (c_awready),
        .s_wdata   (c_wdata),
        .s_wstrb   (c_wstrb),
        .s_wvalid  (c_wvalid),
        .s_wready  (c_wready),
        .s_bresp   (c_bresp),
        .s_bvalid  (c_bvalid),
        .s_bready  (c_bready),
        .s_araddr  (c_araddr),
        .s_arvalid (c_arvalid),
        .s_arready (c_arready),
        .s_rdata   (c_rdata),
        .s_rresp   (c_rresp),
        .s_rvalid  (c_rvalid),
        .s_rready  (c_rready),
        .m_awaddr  (x_awaddr),
        .m_awvalid (x_awvalid),
        .m_awready (x_awready),
        .m_wdata   (x_wdata),
        .m_wstrb   (x_wstrb),
        .m_wvalid  (x_wvalid),
        .m_wready  (x_wready),
        .m_bresp   (x_bresp),
        .m_bvalid  (x_bvalid),
        .m_bready  (x_bready),
        .m_araddr  (x_araddr),
        .m_arvalid (x_arvalid),
        .m_arready (x_arready),
        .m_rdata   (x_rdata),
        .m_rresp   (x_rresp),
        .m_rvalid  (x_rvalid),
        .m_rready  (x_rready)
    );

    // ------------------------------------------------------------------
    // Slave 0: system SRAM
    // ------------------------------------------------------------------
    cvsoc_axil_sram #(.WORDS(4096)) u_sram (
        .clk       (clk),
        .rst_n     (rst_n),
        .s_awaddr  (x_awaddr[0 +: 32]),
        .s_awvalid (x_awvalid[0]),
        .s_awready (x_awready[0]),
        .s_wdata   (x_wdata[0 +: 32]),
        .s_wstrb   (x_wstrb[0 +: 4]),
        .s_wvalid  (x_wvalid[0]),
        .s_wready  (x_wready[0]),
        .s_bresp   (x_bresp[0 +: 2]),
        .s_bvalid  (x_bvalid[0]),
        .s_bready  (x_bready[0]),
        .s_araddr  (x_araddr[0 +: 32]),
        .s_arvalid (x_arvalid[0]),
        .s_arready (x_arready[0]),
        .s_rdata   (x_rdata[0 +: 32]),
        .s_rresp   (x_rresp[0 +: 2]),
        .s_rvalid  (x_rvalid[0]),
        .s_rready  (x_rready[0])
    );

    // ------------------------------------------------------------------
    // Slave 1: APB bridge and peripherals
    // ------------------------------------------------------------------
    localparam int NP = 4;                          // UART, timer, GPIO, simctrl

    logic [NP-1:0]    psel, pready, pslverr;
    logic             penable, pwrite;
    logic [11:0]      paddr;
    logic [31:0]      pwdata;
    logic [3:0]       pstrb;
    logic [32*NP-1:0] prdata;

    cvsoc_axil2apb #(.NP(NP)) u_apb (
        .clk       (clk),
        .rst_n     (rst_n),
        .s_awaddr  (x_awaddr[32 +: 32]),
        .s_awvalid (x_awvalid[1]),
        .s_awready (x_awready[1]),
        .s_wdata   (x_wdata[32 +: 32]),
        .s_wstrb   (x_wstrb[4 +: 4]),
        .s_wvalid  (x_wvalid[1]),
        .s_wready  (x_wready[1]),
        .s_bresp   (x_bresp[2 +: 2]),
        .s_bvalid  (x_bvalid[1]),
        .s_bready  (x_bready[1]),
        .s_araddr  (x_araddr[32 +: 32]),
        .s_arvalid (x_arvalid[1]),
        .s_arready (x_arready[1]),
        .s_rdata   (x_rdata[32 +: 32]),
        .s_rresp   (x_rresp[2 +: 2]),
        .s_rvalid  (x_rvalid[1]),
        .s_rready  (x_rready[1]),
        .slot      ({4'hF, 4'h2, 4'h1, 4'h0}),     // simctrl, GPIO, timer, UART
        .psel      (psel),
        .penable   (penable),
        .pwrite    (pwrite),
        .paddr     (paddr),
        .pwdata    (pwdata),
        .pstrb     (pstrb),
        .prdata    (prdata),
        .pready    (pready),
        .pslverr   (pslverr)
    );

    cvsoc_uart u_uart (
        .clk     (clk),
        .rst_n   (rst_n),
        .psel    (psel[0]),
        .penable (penable),
        .pwrite  (pwrite),
        .paddr   (paddr),
        .pwdata  (pwdata),
        .prdata  (prdata[0 +: 32]),
        .pready  (pready[0]),
        .pslverr (pslverr[0]),
        .tx      (uart_tx)
    );

    cvsoc_timer u_timer (
        .clk     (clk),
        .rst_n   (rst_n),
        .psel    (psel[1]),
        .penable (penable),
        .pwrite  (pwrite),
        .paddr   (paddr),
        .pwdata  (pwdata),
        .prdata  (prdata[32 +: 32]),
        .pready  (pready[1]),
        .pslverr (pslverr[1]),
        .irq     (timer_irq)
    );

    cvsoc_gpio u_gpio (
        .clk      (clk),
        .rst_n    (rst_n),
        .psel     (psel[2]),
        .penable  (penable),
        .pwrite   (pwrite),
        .paddr    (paddr),
        .pwdata   (pwdata),
        .prdata   (prdata[64 +: 32]),
        .pready   (pready[2]),
        .pslverr  (pslverr[2]),
        .gpio_out (gpio_out),
        .gpio_in  (gpio_in)
    );

    cvsoc_simctrl u_simctrl (
        .clk     (clk),
        .rst_n   (rst_n),
        .psel    (psel[3]),
        .penable (penable),
        .pwrite  (pwrite),
        .paddr   (paddr),
        .pwdata  (pwdata),
        .prdata  (prdata[96 +: 32]),
        .pready  (pready[3]),
        .pslverr (pslverr[3]),
        .done    (sim_done),
        .code    (sim_code)
    );

endmodule

tb_boot.sv

// tb_boot: boots cvsoc from the program in main.c.
//
// Pressing Run Simulation builds the C code first, so main.hex always matches the
// sources. The load sequence is the $readmemh line: it fills the TCM inside the CPU
// subsystem, as a debugger or boot ROM would. The serial line is decoded like a
// terminal, and the program ends by writing its result to simulation control.
module tb_boot;

    logic clk = 1'b0;
    logic rst_n = 1'b0;
    always #5 clk = ~clk;                           // 100 MHz

    logic        uart_tx, timer_irq, sim_done;
    logic [31:0] gpio_out, sim_code;

    cvsoc_top u_soc (
        .clk       (clk),
        .rst_n     (rst_n),
        .uart_tx   (uart_tx),
        .gpio_out  (gpio_out),
        .gpio_in   (32'h0000_C0DE),
        .timer_irq (timer_irq),
        .sim_done  (sim_done),
        .sim_code  (sim_code)
    );

    // UART terminal, 8N1 at the reset value of the DIV register
    localparam int BIT_CYCLES = 16;
    logic [7:0] rx_byte;

    initial begin
        forever begin
            @(negedge uart_tx);                     // start bit
            repeat (BIT_CYCLES + BIT_CYCLES / 2) @(posedge clk);
            for (int i = 0; i < 8; i++) begin
                rx_byte[i] = uart_tx;
                repeat (BIT_CYCLES) @(posedge clk);
            end
            $write("%c", rx_byte);
        end
    end

    integer cycles = 0;
    always @(posedge clk)
        if (rst_n) cycles <= cycles + 1;

    initial begin
        for (int i = 0; i < 16384; i++)
            u_soc.u_cpu.tcm[i] = 32'd0;
        $readmemh("main.hex", u_soc.u_cpu.tcm);

        repeat (3) @(posedge clk);
        rst_n <= 1'b1;

        fork
            begin
                wait (sim_done);
                $display("Program finished after %0d cycles, result 0x%08x", cycles, sim_code);
            end
            begin
                repeat (2_000_000) @(posedge clk);
                $display("TIMEOUT: the program did not finish within 2,000,000 cycles");
            end
        join_any
        repeat (4) @(posedge clk);                  // let the final write complete
        $finish;
    end

endmodule

memory_map.json

{
  "version": 1,
  "attached": true,
  "regions": [
    {
      "name": "tcm",
      "kind": "ram",
      "origin": "0x00000000",
      "length": "0x00010000",
      "width": 32
    }
  ],
  "exit_addr": "0x4000F000",
  "console_addr": "0x40000000"
}

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Verilog

268 examples

Name	Topic	Description	Reference	Open
Verilog Strength Modeling	Advanced		Ch#25 : Advanced Topics	Open
Edge Sensitive UDP	Advanced Topics		Ch#25 : Advanced Topics	Open
Level Sensitive UDP	Advanced Topics		Ch#25 : Advanced Topics	Open
Verilog Combo UDP	Advanced Topics		Ch#25 : Advanced Topics	Open
Memory Array: Fill and Read	Arrays	A reg array used as a 16-word memory, filled in a loop and read back	ChipVerify: Verilog Arrays and Memories	Open
Register Vector	Arrays	Verilog vectors get realized into flops that match the size of the variable.	Ch#4 : Arrays & Memories	Open
Verilog Array	Arrays		Ch#4 : Arrays & Memories	Open
assign statement	Assignments	Examples of how 'assign' statements can be written	Ch#6 : Assignments	Open
combo logic with assign	Assignments	Example of using 'assign' statement for combinational logic	Ch#6 : Assignments	Open
Full Adder	Basic Circuits	Example of a full adder with a simple assign statement	Ch#8 : Basic Digital Circuits	Open
AHB Bursts: WRAP4 and INCR4, byte to word	Bus Protocols	WRAP4 bursts of words, halfwords and bytes, then an INCR4 read, with a wait state on the first beat.	Bus Protocols tutorial: AHB Bursts: HTRANS, HBURST and HSIZE	Open
AHB Decoder, Multiplexor and Default Slave	Bus Protocols	One master, two RAM slaves and a default slave, with a data-phase multiplexor select.	Bus Protocols tutorial: AHB with Multiple Slaves	Open
AHB ERROR Response and Burst Cancel	Bus Protocols	An INCR4 write runs into a read-only region; the slave answers with a two-cycle ERROR and the master cancels the last beat.	Bus Protocols tutorial: AHB Wait States and Error Responses	Open
AHB-Lite Memory Slave	Bus Protocols	An AHB-Lite memory slave with byte lanes, configurable wait states and an ERROR response.	Bus Protocols tutorial: Designing an AHB-Lite Memory Slave	Open
AHB-Lite: single and back-to-back transfers	Bus Protocols	A pipelined AHB-Lite master runs single and back-to-back transfers into a 1 KB memory slave.	Bus Protocols tutorial: AHB Transfers and Pipelining	Open
AHB-to-APB bridge	Bus Protocols	An AHB-Lite master reaches an APB completer with wait states and PSLVERR through a bridge.	Bus Protocols tutorial: Bridges: AHB to APB and AXI to APB	Open
APB Completer with Four Registers	Bus Protocols	A minimal APB completer with four 32-bit registers, driven by APB write and read tasks.	Bus Protocols tutorial: APB Bus Protocol	Open
APB Timer Register Block	Bus Protocols	A timer peripheral with RW, RO and write-1-to-clear registers and a level interrupt.	Bus Protocols tutorial: Designing an APB Register Block	Open
APB Wait States and Error Responses	Bus Protocols	An APB3 completer with a slow buffer (two wait states), a read-only ID register and PSLVERR for illegal accesses.	Bus Protocols tutorial: APB Wait States and Error Responses	Open
APB4: PSTRB Byte Writes and PPROT Protection	Bus Protocols	An APB4 completer with a byte-writable register and a Secure-only key register.	Bus Protocols tutorial: APB4 and APB5	Open
AXI4 burst types: FIXED, INCR, WRAP	Bus Protocols	One burst of each type; the slave prints the address of every beat.	Bus Protocols tutorial: AXI Burst Types	Open
AXI4 memory slave	Bus Protocols	A 4 KB AXI4 memory slave with bursts, strobes, a read queue, SLVERR and an exclusive monitor.	Bus Protocols tutorial: Designing an AXI4 Memory Slave	Open
AXI4 read transactions	Bus Protocols	Two read bursts in flight on AR and R, with RREADY backpressure.	Bus Protocols tutorial: AXI Read Transactions	Open
AXI4 responses and exclusive access	Bus Protocols	SLVERR on writes and read beats, and an exclusive access that succeeds and one that fails.	Bus Protocols tutorial: AXI Responses and Exclusive Access	Open
AXI4 transaction IDs and out-of-order reads	Bus Protocols	A slave with two read slots returns a fast read before a slow one when their IDs differ.	Bus Protocols tutorial: AXI Transaction IDs and Ordering	Open
AXI4 write strobes, narrow and unaligned bursts	Bus Protocols	A byte burst and an unaligned word burst; every byte carries its own address.	Bus Protocols tutorial: AXI Write Strobes and Unaligned Transfers	Open
AXI4 write transactions	Bus Protocols	Two write bursts with different IDs on AW, W and B, one with a gap in its data.	Bus Protocols tutorial: AXI Write Transactions	Open
AXI4-Lite interconnect with a default slave	Bus Protocols	One master, two register slaves and a DECERR default slave behind a registered AXI4-Lite interconnect.	Bus Protocols tutorial: Interconnects and Address Maps	Open
AXI4-Lite register slave	Bus Protocols	Four registers behind an AXI4-Lite interface; write address and data arrive in different orders.	Bus Protocols tutorial: Designing an AXI4-Lite Register Slave	Open
AXI4-Stream packet byte counter	Bus Protocols	Counts the bytes of each packet (TKEEP, TLAST) and sends the length on an output stream, with backpressure.	Bus Protocols tutorial: AXI4-Stream	Open
AXI4-Stream skid buffer vs simple register stage	Bus Protocols	A simple register stage and a skid buffer side by side, with a receiver that stalls.	Bus Protocols tutorial: Designing a Stream FIFO and Skid Buffer	Open
AXI4: VALID/READY on all five channels	Bus Protocols	Write data before its address, a slow BREADY and RREADY stalls, with an AXI4 memory slave.	Bus Protocols tutorial: The Five AXI Channels and the VALID/READY Rules	Open
AXI4: outstanding read transactions	Bus Protocols	Four reads from a memory with a 4-cycle latency, with up to four in flight. Set max_reads to 1 to compare.	Bus Protocols tutorial: Why AXI	Open
Address Decoder with Aliasing (bug)	Bus Protocols	The teaching bus with a partial address decoder: the memory also answers at unmapped addresses. Fix the decoder.	Bus Protocols tutorial: Address Decoding and Memory Maps	Open
Bus Arbitration: fixed priority vs round robin	Bus Protocols	Two masters share a bus. A fixed-priority arbiter starves one master; a round-robin arbiter shares the bus evenly.	Bus Protocols tutorial: Arbitration	Open
Bus Transfers: wait states, burst, error	Bus Protocols	A four-beat write burst into a memory with wait states, read-backs, and an error response.	Bus Protocols tutorial: Bus Transfers	Open
Clock Domain Crossing with a Handshake	Bus Protocols	Words cross from a 10 ns to a 14 ns clock domain with a four-phase handshake and two-flip-flop synchronizers.	Bus Protocols tutorial: Bridges and Clock Domain Crossing	Open
Handshakes: four-phase, two-phase, valid/ready	Bus Protocols	Three handshakes on the same clock, side by side, with a stalling valid/ready receiver.	Bus Protocols tutorial: Handshakes	Open
I2C bus monitor (find the bug)	Bus Protocols	A passive I2C monitor decodes the bus into transactions and checks the protocol; the target has a bug.	Bus Protocols tutorial: Verifying Bus and Serial Interfaces	Open
I2C clock stretching	Bus Protocols	An I2C target holds SCL low after each data byte it receives; the controller waits.	Bus Protocols tutorial: I2C Transactions	Open
I2C controller and two register targets	Bus Protocols	An I2C controller writes and reads registers in two targets on an open-drain bus, including a NACK.	Bus Protocols tutorial: How I2C Works	Open
I2C multi-controller arbitration	Bus Protocols	Two I2C controllers start at the same time; bit-by-bit arbitration decides, the loser retries.	Bus Protocols tutorial: I2C Multi-Master and Arbitration	Open
Parallel vs Serial Transfer	Bus Protocols	One byte sent over an 8-bit parallel link and over a 1-bit serial line, LSB first.	Bus Protocols tutorial: Parallel vs Serial, Synchronous vs Asynchronous	Open
Pipelining and Outstanding Transactions	Bus Protocols	Eight reads from a memory with a 3-cycle latency, with 1, 2 and 4 reads allowed in flight.	Bus Protocols tutorial: Pipelining and Outstanding Transactions	Open
Quad SPI flash read	Bus Protocols	A quad SPI master reads four bytes from a flash model with the Quad Output Fast Read command 0x6B.	Bus Protocols tutorial: Dual and Quad SPI	Open
SPI master and register slave, any mode	Bus Protocols	An SPI master writes and reads registers in an SPI slave; set CPOL and CPHA to try all four modes.	Bus Protocols tutorial: How SPI Works	Open
SPI with two slaves	Bus Protocols	One SPI master and two slaves sharing SCLK, MOSI and a tri-state MISO, with a chip select each.	Bus Protocols tutorial: SPI Slaves and Multiple Devices	Open
Self-Checking AHB Testbench (find the bug)	Bus Protocols	Random bursts, a byte-level model, a scoreboard and protocol checks find a byte-lane bug in an AHB-Lite memory slave.	Bus Protocols tutorial: Verifying AHB	Open
Self-Checking APB Testbench (find the bug)	Bus Protocols	A reference model, scoreboard and protocol checks find an address-decode bug in an APB register block.	Bus Protocols tutorial: Verifying an APB Slave	Open
Self-checking AXI testbench (find the bug)	Bus Protocols	Random AXI4 bursts, a byte-level scoreboard and protocol checks find a bug in an AXI4 memory slave.	Bus Protocols tutorial: Verifying AXI	Open
Shared Bus vs Crossbar	Bus Protocols	Two masters and two slaves: a shared bus allows one transfer per cycle, a crossbar one per slave.	Bus Protocols tutorial: Interconnects	Open
Simple Bus: master, decoder, two slaves	Bus Protocols	A small teaching bus with a register slave, a memory slave with one wait state, and an error for unmapped addresses.	Bus Protocols tutorial: What Is a Bus?	Open
UART baud rate mismatch	Bus Protocols	The transmitter runs 6 percent slow: watch the receiver samples drift and the framing errors.	Bus Protocols tutorial: Designing a UART Receiver	Open
UART parity and CTS flow control	Bus Protocols	Even parity catches a bit flipped by noise; CTS pauses the transmitter between frames.	Bus Protocols tutorial: UART Parity, Flow Control and Physical Layers	Open
UART transmitter and receiver loopback	Bus Protocols	A UART transmitter sends three bytes over one wire to a UART receiver (8N1, 16 clocks per bit).	Bus Protocols tutorial: How UART Works	Open
Nested ifdef	Conditional Compilation		Ch#24 : Compiler Directives	Open
ifdef Design Example	Conditional Compilation	Use ifdef to include the code only if the macro is defined in compilation args	Ch#24 : Compiler Directives	Open
ifdef elsif Macro	Conditional Compilation		Ch#24 : Compiler Directives	Open
ifndef elsif Macro	Conditional Compilation		Ch#24 : Compiler Directives	Open
'if else if' synthesis	Conditional Statements	Example demonstrating how 'if else if' results in a priority encoder	Ch#11 : Conditional Statements	Open
'if else' multiple statements	Conditional Statements	'if else' block for multiple statements within the 'if' and 'else' part	Ch#11 : Conditional Statements	Open
'if else' single statement	Conditional Statements	Simple 'if' followed by the 'else' part for single statements within the if and else part	Ch#11 : Conditional Statements	Open
'if' without 'else'	Conditional Statements	'if' statement without an 'else' part	Ch#11: Conditional Statements	Open
'if' without 'else' multiple statements	Conditional Statements	Multiple statements are put within 'begin' and 'end'	Ch#11 : Conditional Statements	Open
'if' without 'else' synthesis	Conditional Statements	Example shows how 'if' block without 'else' can form a latch	Ch#11: Conditional Statements	Open
Case Statement	Conditional Statements		Ch#11 : Conditional Statements	Open
4-bit Counter	Counters	Example of a simple 4-bit counter	Ch#14: Counters	Open
Gray Counter	Counters	Example of a simple parameterizable gray counter	Ch#14 : Gray Counter	Open
Johnson Counter	Counters	Example of a Johnson Counter	Ch#14 : Counters	Open
Mod-N Counter	Counters	Example of a MOD-N counter	Ch#14 : Counters	Open
Ring Counter	Counters	Example of a simple ring counter	Ch#14 : Counters	Open
Signal Concatenation	Data Types	Example of wire concatenation using 'assign' statement	Ch#3 : Data Types & Operators	Open
Delay Control	Delay Control	Shows how delay values can be applied in multiple ways	Ch#21 : Timing & Delays	Open
Event 'or' Operator	Delay Control	Use 'or' operator to specify conditonal events	Ch#21 Timing & Delays	Open
Event Control	Delay Control	Example of using @ control for event based sync	Ch#21 : Timing & Delays	Open
Implicit Event Expression List	Delay Control	Use * in the sensitivity list to include all signals that the block needs to be listening to	Ch#21 : Timing & Delays	Open
Level Sensitive Event Control	Delay Control	Shows how @ operator can be used to make execution wait until a variable reaches a specific value	Ch#21 : Timing & Delays	Open
Posedge Detector	Detectors	Example of a simple positive edge detector	Ch#17 : Edge Detectors	Open
$stop $finish: $finish	Examples	Runnable example from the Verilog $stop $finish tutorial ($finish)	ChipVerify: Verilog $stop $finish	Open
$stop $finish: $stop	Examples	Runnable example from the Verilog $stop $finish tutorial ($stop)	ChipVerify: Verilog $stop $finish	Open
- Quick Review: Data Types	Examples	Runnable example from the Verilog - Quick Review tutorial (Data Types)	ChipVerify: Verilog - Quick Review	Open
4 to 1 Multiplexer/Mux: Testbench	Examples	Runnable example from the Verilog 4 to 1 Multiplexer/Mux tutorial (Testbench)	ChipVerify: Verilog 4 to 1 Multiplexer/Mux	Open
4x1 Multiplexer with 'assign'	Examples	Shows how to code a multiplexer circuit with 'assign' statement	Ch#8: Basic Digital Circuits	Open
4x1 Multiplexer with 'case'	Examples	Shows how to infer a multiplexer using 'case' statement	Ch#8: Basic Digital Circuits	Open
Arithmetic Operators: Expression Bit Lengths and Sizing	Examples	Runnable example from the Verilog Arithmetic Operators tutorial (Expression Bit Lengths and Sizing)	ChipVerify: Verilog Arithmetic Operators	Open
Arithmetic Operators: Expression Bit Lengths and Sizing	Examples	Runnable example from the Verilog Arithmetic Operators tutorial (Expression Bit Lengths and Sizing)	ChipVerify: Verilog Arithmetic Operators	Open
Assignments: Common Beginner Mistakes	Examples	Runnable example from the Verilog Assignments tutorial (Common Beginner Mistakes)	ChipVerify: Verilog Assignments	Open
Assignments: Common Beginner Mistakes	Examples	Runnable example from the Verilog Assignments tutorial (Common Beginner Mistakes)	ChipVerify: Verilog Assignments	Open
Assignments: Variable Declaration Assignment	Examples	Runnable example from the Verilog Assignments tutorial (Variable Declaration Assignment)	ChipVerify: Verilog Assignments	Open
Assignments: Variable Declaration Assignment	Examples	Runnable example from the Verilog Assignments tutorial (Variable Declaration Assignment)	ChipVerify: Verilog Assignments	Open
Blocking & Non-Blocking: Non-Blocking Assignments with Delays	Examples	Runnable example from the Verilog Blocking & Non-Blocking tutorial (Non-Blocking Assignments with Delays)	ChipVerify: Verilog Blocking & Non-Blocking	Open
Blocking Assignments	Examples	Runnable example from the Verilog Blocking & Non-Blocking tutorial (Blocking Assignments)	ChipVerify: Verilog Blocking & Non-Blocking	Open
Blocking Assignments	Examples	Runnable example from the Verilog Blocking & Non-Blocking tutorial (Blocking Assignments)	ChipVerify: Verilog Blocking & Non-Blocking	Open
Blocking Assignments	Examples	Runnable example from the Verilog Blocking & Non-Blocking tutorial (Blocking Assignments)	ChipVerify: Verilog Blocking & Non-Blocking	Open
Clock Generator: Simple Clock Generation	Examples	Runnable example from the Verilog Clock Generator tutorial (Simple Clock Generation)	ChipVerify: Verilog Clock Generator	Open
Clock Generator: Verilog Clock Generator	Examples	Runnable example from the Verilog Clock Generator tutorial (Verilog Clock Generator)	ChipVerify: Verilog Clock Generator	Open
Combinational Logic with always: Testbench	Examples	Runnable example from the Combinational Logic with always tutorial (Testbench)	ChipVerify: Combinational Logic with always	Open
Combinational Logic with always: Testbench	Examples	Runnable example from the Combinational Logic with always tutorial (Testbench)	ChipVerify: Combinational Logic with always	Open
Combinational Logic with always: Testbench	Examples	Runnable example from the Combinational Logic with always tutorial (Testbench)	ChipVerify: Combinational Logic with always	Open
Combinational Logic with always: Testbench	Examples	Runnable example from the Combinational Logic with always tutorial (Testbench)	ChipVerify: Combinational Logic with always	Open
Combinational Logic with always: Testbench	Examples	Runnable example from the Combinational Logic with always tutorial (Testbench)	ChipVerify: Combinational Logic with always	Open
Combinational Logic with always: Testbench	Examples	Runnable example from the Combinational Logic with always tutorial (Testbench)	ChipVerify: Combinational Logic with always	Open
Combinational Logic with assign: Testbench	Examples	Runnable example from the Combinational Logic with assign tutorial (Testbench)	ChipVerify: Combinational Logic with assign	Open
Combinational Logic with assign: Testbench	Examples	Runnable example from the Combinational Logic with assign tutorial (Testbench)	ChipVerify: Combinational Logic with assign	Open
Combinational Logic with assign: Testbench	Examples	Runnable example from the Combinational Logic with assign tutorial (Testbench)	ChipVerify: Combinational Logic with assign	Open
Combinational Logic with assign: Testbench	Examples	Runnable example from the Combinational Logic with assign tutorial (Testbench)	ChipVerify: Combinational Logic with assign	Open
Combinational Logic with assign: Testbench	Examples	Runnable example from the Combinational Logic with assign tutorial (Testbench)	ChipVerify: Combinational Logic with assign	Open
Combinational Logic with assign: Testbench	Examples	Runnable example from the Combinational Logic with assign tutorial (Testbench)	ChipVerify: Combinational Logic with assign	Open
Concatenation: Nested Replication	Examples	Runnable example from the Verilog Concatenation tutorial (Nested Replication)	ChipVerify: Verilog Concatenation	Open
Concatenation: Replication Operator	Examples	Runnable example from the Verilog Concatenation tutorial (Replication Operator)	ChipVerify: Verilog Concatenation	Open
Concatenation: Replication Operator	Examples	Runnable example from the Verilog Concatenation tutorial (Replication Operator)	ChipVerify: Verilog Concatenation	Open
Conversion Functions: Passing Real Values Through Ports	Examples	Runnable example from the Verilog Conversion Functions tutorial (Passing Real Values Through Ports)	ChipVerify: Verilog Conversion Functions	Open
D Flip-Flop: Testbench	Examples	Runnable example from the Verilog D Flip-Flop tutorial (Testbench)	ChipVerify: Verilog D Flip-Flop	Open
Data Types: Datatypes Example	Examples	Runnable example from the Verilog Data Types tutorial (Datatypes Example)	ChipVerify: Verilog Data Types	Open
Data Types: Verilog Strings	Examples	Runnable example from the Verilog Data Types tutorial (Verilog Strings)	ChipVerify: Verilog Data Types	Open
Delay Control: Implicit Event Expression List	Examples	Runnable example from the Verilog Delay Control tutorial (Implicit Event Expression List)	ChipVerify: Verilog Delay Control	Open
Delay Control: Implicit Event Expression List	Examples	Runnable example from the Verilog Delay Control tutorial (Implicit Event Expression List)	ChipVerify: Verilog Delay Control	Open
Delay Control: Named Events	Examples	Runnable example from the Verilog Delay Control tutorial (Named Events)	ChipVerify: Verilog Delay Control	Open
Display Tasks: Verilog Escape Sequences	Examples	Runnable example from the Verilog Display Tasks tutorial (Verilog Escape Sequences)	ChipVerify: Verilog Display Tasks	Open
Display Tasks: Verilog Format Specifiers	Examples	Runnable example from the Verilog Display Tasks tutorial (Verilog Format Specifiers)	ChipVerify: Verilog Display Tasks	Open
Display Tasks: Verilog Strobes	Examples	Runnable example from the Verilog Display Tasks tutorial (Verilog Strobes)	ChipVerify: Verilog Display Tasks	Open
Display Tasks: Verilog Strobes	Examples	Runnable example from the Verilog Display Tasks tutorial (Verilog Strobes)	ChipVerify: Verilog Display Tasks	Open
File IO Operations: Detecting EOF	Examples	Runnable example from the Verilog File IO Operations tutorial (Detecting EOF)	ChipVerify: Verilog File IO Operations	Open
File IO Operations: Formatting data to a string	Examples	Runnable example from the Verilog File IO Operations tutorial (Formatting data to a string)	ChipVerify: Verilog File IO Operations	Open
File IO Operations: How to write files	Examples	Runnable example from the Verilog File IO Operations tutorial (How to write files)	ChipVerify: Verilog File IO Operations	Open
File IO Operations: Multiple arguments to fdisplay	Examples	Runnable example from the Verilog File IO Operations tutorial (Multiple arguments to fdisplay)	ChipVerify: Verilog File IO Operations	Open
File IO Operations: Opening and closing files	Examples	Runnable example from the Verilog File IO Operations tutorial (Opening and closing files)	ChipVerify: Verilog File IO Operations	Open
Gate Delay: Inertial Delay: Short Pulses Are Filtered	Examples	Runnable example from the Verilog Gate Delay tutorial (Inertial Delay: Short Pulses Are Filtered)	ChipVerify: Verilog Gate Delay	Open
Gate Level Examples: Example #1: 2x1 Multiplexer	Examples	Runnable example from the Verilog Gate Level Examples tutorial (Example #1: 2x1 Multiplexer)	ChipVerify: Verilog Gate Level Examples	Open
Gate Level Examples: Full Adder	Examples	Runnable example from the Verilog Gate Level Examples tutorial (Full Adder)	ChipVerify: Verilog Gate Level Examples	Open
Inter and Intra Assignment Delay: Inter-assignment Delays	Examples	Runnable example from the Verilog Inter and Intra Assignment Delay tutorial (Inter-assignment Delays)	ChipVerify: Verilog Inter and Intra Assignment Delay	Open
Inter and Intra Assignment Delay: Intra-assignment Delays	Examples	Runnable example from the Verilog Inter and Intra Assignment Delay tutorial (Intra-assignment Delays)	ChipVerify: Verilog Inter and Intra Assignment Delay	Open
Interview Questions Set 2: How can you generate a sine wave using the Verilog co	Examples	Runnable example from the Verilog Interview Questions Set 2 tutorial (How can you generate a sine wave using the Verilog coding style ?)	ChipVerify: Verilog Interview Questions Set 2	Open
Interview Questions Set 2: What is verilog $random ?	Examples	Runnable example from the Verilog Interview Questions Set 2 tutorial (What is verilog $random ?)	ChipVerify: Verilog Interview Questions Set 2	Open
Interview Questions Set 3: What is $time in Verilog?	Examples	Runnable example from the Verilog Interview Questions Set 3 tutorial (What is $time in Verilog?)	ChipVerify: Verilog Interview Questions Set 3	Open
Interview Questions Set 5: Same variable used in two loops running simultaneousl	Examples	Runnable example from the Verilog Interview Questions Set 5 tutorial (Same variable used in two loops running simultaneously)	ChipVerify: Verilog Interview Questions Set 5	Open
Interview Questions Set 5: Same variable used in two loops running simultaneousl	Examples	Runnable example from the Verilog Interview Questions Set 5 tutorial (Same variable used in two loops running simultaneously)	ChipVerify: Verilog Interview Questions Set 5	Open
Interview Questions Set 7: How to generate two different clocks in testbench ?	Examples	Runnable example from the Verilog Interview Questions Set 7 tutorial (How to generate two different clocks in testbench ?)	ChipVerify: Verilog Interview Questions Set 7	Open
Interview Questions Set 7: Illustrate the side-effects of a function return type	Examples	Runnable example from the Verilog Interview Questions Set 7 tutorial (Illustrate the side-effects of a function return type without a range.)	ChipVerify: Verilog Interview Questions Set 7	Open
Interview Questions Set 7: What is #0 in Verilog and its usage?	Examples	Runnable example from the Verilog Interview Questions Set 7 tutorial (What is #0 in Verilog and its usage?)	ChipVerify: Verilog Interview Questions Set 7	Open
Interview Questions Set 8: Write simple Verilog code to generate 100MHz clock.	Examples	Runnable example from the Verilog Interview Questions Set 8 tutorial (Write simple Verilog code to generate 100MHz clock.)	ChipVerify: Verilog Interview Questions Set 8	Open
Interview Questions Set 9: Write Verilog code to store fractional number	Examples	Runnable example from the Verilog Interview Questions Set 9 tutorial (Write Verilog code to store fractional number)	ChipVerify: Verilog Interview Questions Set 9	Open
Introduction to Verilog: Testbench code	Examples	Runnable example from the Introduction to Verilog tutorial (Testbench code)	ChipVerify: Introduction to Verilog	Open
Introduction to Verilog: Testbench code	Examples	Runnable example from the Introduction to Verilog tutorial (Testbench code)	ChipVerify: Introduction to Verilog	Open
JK Flip Flop: Testbench	Examples	Runnable example from the JK Flip Flop tutorial (Testbench)	ChipVerify: JK Flip Flop	Open
Operators: Bitwise OR (\|) Truth Table	Examples	Runnable example from the Verilog Operators tutorial (Bitwise OR (\|) Truth Table)	ChipVerify: Verilog Operators	Open
Operators: Verilog Arithmetic Operators	Examples	Runnable example from the Verilog Operators tutorial (Verilog Arithmetic Operators)	ChipVerify: Verilog Operators	Open
Operators: Verilog Arithmetic Operators	Examples	Runnable example from the Verilog Operators tutorial (Verilog Arithmetic Operators)	ChipVerify: Verilog Operators	Open
Operators: Verilog Arithmetic Operators	Examples	Runnable example from the Verilog Operators tutorial (Verilog Arithmetic Operators)	ChipVerify: Verilog Operators	Open
Operators: Verilog Shift Operators	Examples	Runnable example from the Verilog Operators tutorial (Verilog Shift Operators)	ChipVerify: Verilog Operators	Open
Priority Encoder: Testbench	Examples	Runnable example from the Verilog Priority Encoder tutorial (Testbench)	ChipVerify: Verilog Priority Encoder	Open
Ripple Counter: Testbench	Examples	Runnable example from the Verilog Ripple Counter tutorial (Testbench)	ChipVerify: Verilog Ripple Counter	Open
Scheduling Semantics: Event Processing Flow	Examples	Runnable example from the Verilog Scheduling Semantics tutorial (Event Processing Flow)	ChipVerify: Verilog Scheduling Semantics	Open
Sequential Logic with always: Testbench	Examples	Runnable example from the Sequential Logic with always tutorial (Testbench)	ChipVerify: Sequential Logic with always	Open
Sequential Logic with always: Testbench	Examples	Runnable example from the Sequential Logic with always tutorial (Testbench)	ChipVerify: Sequential Logic with always	Open
Sequential Logic with always: Testbench	Examples	Runnable example from the Sequential Logic with always tutorial (Testbench)	ChipVerify: Sequential Logic with always	Open
Strength: Modeling an Open-Drain Bus	Examples	Runnable example from the Verilog Strength tutorial (Modeling an Open-Drain Bus)	ChipVerify: Verilog Strength	Open
Synchronous FIFO Verilog Code	Examples	Runnable example from the Synchronous FIFO tutorial (Synchronous FIFO Verilog Code)	ChipVerify: Synchronous FIFO	Open
Task: Disable Task	Examples	Runnable example from the Verilog Task tutorial (Disable Task)	ChipVerify: Verilog Task	Open
Task: Global tasks	Examples	Runnable example from the Verilog Task tutorial (Global tasks)	ChipVerify: Verilog Task	Open
Task: Global tasks	Examples	Runnable example from the Verilog Task tutorial (Global tasks)	ChipVerify: Verilog Task	Open
Task: Static Task	Examples	Runnable example from the Verilog Task tutorial (Static Task)	ChipVerify: Verilog Task	Open
Task: Using Tasks in Testbenches	Examples	Runnable example from the Verilog Task tutorial (Using Tasks in Testbenches)	ChipVerify: Verilog Task	Open
Testbench Simulation: Regions in event queue	Examples	Runnable example from the Verilog Testbench Simulation tutorial (Regions in event queue)	ChipVerify: Verilog Testbench Simulation	Open
Testbench Simulation: Regions in event queue	Examples	Runnable example from the Verilog Testbench Simulation tutorial (Regions in event queue)	ChipVerify: Verilog Testbench Simulation	Open
Timeformat: %t vs %0t and the Minimum Field Width	Examples	Runnable example from the Verilog Timeformat tutorial (%t vs %0t and the Minimum Field Width)	ChipVerify: Verilog Timeformat	Open
Timescale Scope: Default timescale	Examples	Runnable example from the Verilog Timescale Scope tutorial (Default timescale)	ChipVerify: Verilog Timescale Scope	Open
Timescale Scope: Standard timescale scope	Examples	Runnable example from the Verilog Timescale Scope tutorial (Standard timescale scope)	ChipVerify: Verilog Timescale Scope	Open
Timescale: Example #1: 1ns/1ns	Examples	Runnable example from the Verilog Timescale tutorial (Example #1: 1ns/1ns)	ChipVerify: Verilog Timescale	Open
Timescale: Example #2: 10ns/1ns	Examples	Runnable example from the Verilog Timescale tutorial (Example #2: 10ns/1ns)	ChipVerify: Verilog Timescale	Open
Timescale: Multiple Timescales in One Design	Examples	Runnable example from the Verilog Timescale tutorial (Multiple Timescales in One Design)	ChipVerify: Verilog Timescale	Open
Timescale: Printing Time: $time, $realtime and $timeformat	Examples	Runnable example from the Verilog Timescale tutorial (Printing Time: $time, $realtime and $timeformat)	ChipVerify: Verilog Timescale	Open
VCD Dump: $dumpfile	Examples	Runnable example from the Verilog VCD Dump tutorial ($dumpfile)	ChipVerify: Verilog VCD Dump	Open
VCD Dump: $dumplimit	Examples	Runnable example from the Verilog VCD Dump tutorial ($dumplimit)	ChipVerify: Verilog VCD Dump	Open
VCD Dump: $dumpon, $dumpoff	Examples	Runnable example from the Verilog VCD Dump tutorial ($dumpon, $dumpoff)	ChipVerify: Verilog VCD Dump	Open
VCD Dump: A Complete Example	Examples	Runnable example from the Verilog VCD Dump tutorial (A Complete Example)	ChipVerify: Verilog VCD Dump	Open
VCD: A Complete Example	Examples	Runnable example from the Verilog VCD tutorial (A Complete Example)	ChipVerify: Verilog VCD	Open
`define Macro: Macro Example	Examples	Runnable example from the Verilog `define Macro tutorial (Macro Example)	ChipVerify: Verilog `define Macro	Open
initial Block: Common Beginner Mistakes	Examples	Runnable example from the Verilog initial Block tutorial (Common Beginner Mistakes)	ChipVerify: Verilog initial Block	Open
File IO Operations	File IO	How to write into and read from files	Ch#23 : Testbench Features	Open
T Flip Flop	Flip Flops		Ch#10 : Flip Flops & Latches	Open
D Latch	Flops & Latches	Example of a D Latch	D Latch	Open
Recursive Functions	Functions	Example of a recursive function by computing a factorial of a number	Ch#13 : Functions & Tasks	Open
Gate Delay	Gate Level Modeling	Shows how to model in single delay format	Ch#20 : Gate Level Modeling	Open
Gate Three Delay	Gate Level Modeling	Three delay format	Ch#20 : Gate Level Modeling	Open
Gate Two Delay	Gate Level Modeling	Shows how to model rise/fall times for gates	Ch#20 : Gate Level Modeling	Open
Min/Typ/Max Delays	Gate Level Modeling	How to specify min/typ/max delays for rise/fall transitions	Ch#20 : Gate Level Modeling	Open
And/Or/Xor Gates	Gate Level Simulation	Example of 'and', 'or', and 'xor' gates	Ch#20: GLS	Open
And/Or/Xor with N Inputs	Gate Level Simulation	These gates can have more than 2 inputs	Ch#20: GLS	Open
Buf/Not Gates	Gate Level Simulation	Example of 'buf' and 'not' gates	GLS	Open
Buf/Not Multiple Outputs	Gate Level Simulation	Example of 'buf' and 'not' with multiple output ports driven by a single input	GLS	Open
Decoder with Gates	Gate Level Simulation	Example of a decoder using simple gates	Ch#21 : Gate Level Modeling	Open
Nand/Nor/Xnor Gates	Gate Level Simulation	Example of 'nand', 'nor', and 'xnor' gates	Ch#20: GLS	Open
Priorty Encoder with Gates	Gate Level Simulation	Example of a priority encoder implemented using simple gates	Ch#21 : Gate Level Modeling	Open
Generate Case	Generate	How to use a case statement inside a generate block	Ch#12 : Loops & Generate	Open
Generate If else	Generate	Use of if else condition inside a generate block	Ch#12 : Loops & Generate	Open
Generate for Loop	Generate	Example of how to instantiate multiple times with a generate for loop block	Ch#12 : Loops & Generate	Open
Hello World	Intro	A simple simulation to print Hello World in Verilog and get started !		Open
8-bit Shift Register	Loops	Example of using a for loop to create a shift register	Ch#12 : Loops & Generate	Open
$clog2 Math Function	Math Functions	Example of $clog2	Ch#28 : Utility Functions	Open
$clog2: Memory Address Width	Math Functions	A parameterized memory whose address width comes from $clog2(DEPTH), with a small testbench	ChipVerify: Verilog Math Functions	Open
Verilog Math Functions	Math Functions	Examples of math related system tasks	Ch#28 : Utility Functions	Open
Memory Example	Memories		Ch#4 : Arrays & Memories	Open
Single Port Sync RAM	Memory Elements		Ch#18 : Memory Elements	Open
Synchronous FIFO	Memory Elements	Example of a synchronous fifo	Ch#18 : Memory Elements	Open
Hierarchical Referencing	Misc	Example of hierarchical referencing using dot (.) operator	Ch#25 : Advanced Topics	Open
Module Instantiation Ordered Ports	Module	Instantiation of module with ordered port list	Ch#2 : Basic Syntax & Structure	Open
DFF Module Example	Modules	Example of a module with input and output ports	Ch#2: Verilog Module	Open
Module Instantiation	Modules	Connect module instances to form bigger blocks	Ch#2: Verilog Module	Open
Net Types: wire, wor and wand Resolution	Net Types	Two drivers on a wire, wor and wand net show how each net type resolves conflicts	ChipVerify: Verilog Net Types	Open
Tri Nets	Net Types	Example that shows how 'tri0' and 'tri1' nets behave	Ch#3 : Data Types & Operators	Open
Wired Net Types	Net Types	Example that shows how 'wor', 'wand', 'trior' and 'triand' behave	Ch#3 : Data Types & Operators	Open
Arithmetic Operators	Operators	Simple arithmetic operators for addition, subtraction, etc	Ch#3: Data Types & Operators	Open
Bitwise Operators	Operators	Bitwise operators like &, \|	Ch#3: Data Types & Operators	Open
Equality Operators	Operators	Equality operators like ==, !==	Ch#3: Data Types & Operators	Open
Logical Operators	Operators	Logical operators like &&, \|\|	Ch#3: Data Types & Operators	Open
Relational Operators	Operators	Relational operators like <, >, <=, >=	ChipVerify	Open
Shift Operators	Operators	Shift operators like <<, >>	Ch #3: Data Types & Operators	Open
Localparam Part Select	Parameters	Example of how localparams can have expressions that contain part-select	Ch#4 : Array Memories & Parameters	Open
PD: 16x16 Multiplier (about 1,300 cells)	Physical Design	A registered 16x16 multiplier: a bigger design for floorplan, routing-layer and placement experiments; fits the free PnR cell limit.	Physical Design tutorial: The Metal Stack: Layers, Vias and Pitches	Open
PD: 32-bit Adder, One Stage	Physical Design	A 32-bit adder between input and output registers (97 flip-flops). In the lab flow it misses 6 ns and closes at 7 ns with a setup margin.	Physical Design tutorial: Project: Closing Timing on a Pipelined Adder	Open
PD: 32-bit Adder, Two Pipeline Stages	Physical Design	The same adder split into two stages of 16 bits (146 flip-flops). Misses 5 ns by 0.01 ns in the lab flow; with a 0.3 ns setup margin it closes at 5 ns and at 4 …	Physical Design tutorial: Project: Closing Timing on a Pipelined Adder	Open
PD: 8-bit Counter, First Place and Route	Physical Design	An 8-bit counter to take through synthesis and Place and Route: 28 cells, about 300 um2 at 50 % utilization.	Physical Design tutorial: Your First Place and Route Run	Open
PD: SRAM Macro Wrapper (synthesis view)	Physical Design	A wrapper around the sky130 OpenRAM SRAM sky130_sram_1rw1r_44x64_8, kept as a black box in synthesis. Place and Route with the macro is a PRO feature; use 30 % …	Physical Design tutorial: Macro Placement: Halos and Channels	Open
PD: UART Transmitter (reset synchronizer, no tie cells needed)	Physical Design	A 115200-baud UART transmitter with a two-flop reset synchronizer: 27 flip-flops, about 1,200 um2. Routes in the lab at 10 ns down to about 2 ns.	Physical Design tutorial: Project: Place and Route a UART Transmitter	Open
Verilog ANSI Ports	Ports	How ports are declared in Verilog 2001 ANSI-C style	Ch#3 : Basic Syntax & Structure	Open
Verilog non-ANSI Ports	Ports	How ports are declared based on Verilog 1995 non-ANSI style	Ch#2 : Basic Syntax & Structure	Open
$finish aborts simulation	Procedural Blocks	Use early $finish to terminate simulation even when there are multiple other initial blocks still running	Ch#5: Procedural Blocks	Open
Always Block for Combinational Logic	Procedural Blocks	Example of a simple combinational logic written with 'always' block	Ch#5: Procedural Blocks	Open
Block Statements	Procedural Blocks	Example of using 'begin end' to form blocks that are executed sequentially	Ch#5 : Procedural Blocks	Open
Initial Block with Delays	Procedural Blocks	initial block with delays #	Ch#5: Procedural Blocks	Open
Multiple initial Blocks	Procedural Blocks	Example of multiple initial blocks within the same module : https://www.chipverify.com/verilog/verilog-initial-block	Ch#5: Procedural Blocks	Open
$random Full Range	Random	Example that shows how to get any value within a range	Ch#23 : Testbench Features	Open
$random Positive Range	Random	Use $random to get only positive range of values	Ch#23 : Testbench Features	Open
$random different seeds	Random	When $random is called without a fixed seed	Ch#23 : Testbench Features	Open
$random with seed arg	Random	Shows how $random with a seed arg gives the same value everytime	Ch#23 : Testbench Features	Open
N-bit Bidirectional Shift Register	Shift Registers	Example of a parameterizable bi-directional shift register	Ch#15 : Shift Registers	Open
1011 Sequence Detector	State Machines	Example of 1011 sequence detector	Ch#16 : State Machines	Open
Pattern Detector 110101	State Machines	Example of a pattern detector for 110101	Ch#16 : State Machines	Open
STA 8-Bit Adder: One Stage	Static Timing Analysis	An 8-bit adder between two register stages; the carry chain limits the clock to about 2.95 ns	STA tutorial: Timing-Aware RTL	Open
STA 8-Bit Adder: Two Pipeline Stages	Static Timing Analysis	The same adder split into a low-nibble stage and a high-nibble stage; it runs at about 1.5 ns	STA tutorial: Timing-Aware RTL	Open
STA Asynchronous Reset: Recovery and Removal	Static Timing Analysis	A flip-flop with an asynchronous reset and the recovery and removal checks of the reset release	STA tutorial: Recovery and Removal Checks	Open
STA Chain: Clock Skew Between Two Flip-Flops	Static Timing Analysis	Two flip-flops with a logic cone between them that fails setup at 1.0 ns; delay the capture clock to fix it	STA tutorial: Clock Skew	Open
STA Clock Divider and Generated Clock	Static Timing Analysis	A divide-by-2 flip-flop makes a clock that STA does not know until you define it as a generated clock	STA tutorial: Generated Clocks	Open
STA Clock Gate: Gating Check	Static Timing Analysis	An AND gate in the clock path with the enable from a rising-edge flip-flop violates the gating hold check	STA tutorial: Clock Gating Checks	Open
STA Clock Mux: Exclusive Clocks	Static Timing Analysis	A multiplexer selects between a 2.0 ns and a 3.0 ns clock; remove the clock pairs that cannot happen	STA tutorial: Clock Muxes	Open
STA DDR Input: Both Clock Edges	Static Timing Analysis	Data that changes on both edges of the clock needs an input delay for each edge	STA tutorial: Source-Synchronous and DDR Timing	Open
STA Demo: Two Flip-Flops and Two Outputs	Static Timing Analysis	The small design of the STA tutorial: all four path types, with a 2.0 ns clock and 0.4 ns port delays	STA tutorial: Your First OpenSTA Run	Open
STA Half-Cycle Path: Rising to Falling Edge	Static Timing Analysis	A rising-edge flip-flop feeding a falling-edge flip-flop; the duty cycle sets the time of the path	STA tutorial: Half-Cycle Paths	Open
STA Two Clocks: Clock Groups	Static Timing Analysis	A path from a 2.0 ns clock to a 3.0 ns clock, and what an asynchronous clock group removes	STA tutorial: Clock Groups	Open
STA UART Transmitter: Failing Timing at 3.4 ns	Static Timing Analysis	A 100 MHz, 115200 baud UART transmitter that fails setup and removal at the slow corner with a 3.4 ns clock	STA tutorial: Writing SDC for the UART Project	Open
STA UART Transmitter: Timing Closed at 3.4 ns	Static Timing Analysis	The UART with two 5-bit counters, a registered tick and a reset synchronizer; it meets timing at all three corners	STA tutorial: Capstone, Closing Timing on a Pipelined UART	Open
Bidirectional tran Switch	Switch Level Modeling		Ch#20 : Gate Level Modeling	Open
Bidirectional tranif0 Switch	Switch Level Modeling		Ch#20 : Gate Level Modeling	Open
Bidirectional tranif1 Switch	Switch Level Modeling		Ch#20 : Gate Level Modeling	Open
CMOS Switch	Switch Level Modeling	Example of a CMOS switch	Ch#20 : Gate Level Modeling	Open
NMOS/PMOS Modeling	Switch Level Modeling	Example of using nmos/pmos	Ch#20 : Gate Level Modeling	Open
Supplies Power & Ground	Switch Level Modeling		Ch#20 : Gate Level Modeling	Open
Verilog Task	Tasks		Ch#13 : Functions & Tasks	Open
Testbench Simulation	Testbench	Example of a simulation where a signal is driven different values after certain delays	Ch#22 : Testbench	Open
Verilog $random	Testbench	Example of how to use $random to generate random numbers in a testbench	Ch#23 : Adv Testbench Features	Open
Verilog Display Tasks	Testbench	Shows the difference between $display and $write	Ch#23 : Testbench	Open
Clock Generator	Timing	Example of clock generator	Ch#19 : Clocks & Timing	Open
Timescale	Timing & Delays		Ch#21 : Timing & Delays	Open
Verilog Timeformat	Timing & Delays		Ch#21 : Timing & Delays	Open
Verilog Timescale	Timing & Delays		Ch#21 : Timing & Delays	Open
Verilog Timescale Scope	Timing & Delays		Ch#21 : Timing & Delays	Open
Part Selects	Vectors	Example of a part-select on vector	Ch#4 : Data Types	Open

SystemVerilog

378 examples

Name	Topic	Description	Reference	Open
$unit Compilation Scope: $unit:: Doesn't Add Forward Visibility	Advanced Features	Runnable example from the SystemVerilog $unit Compilation Scope tutorial ($unit:: Doesn't Add Forward Visibility)	ChipVerify: SystemVerilog $unit Compilation Scope	Open
$unit Compilation Scope: Accessing It Explicitly with $unit::	Advanced Features	Runnable example from the SystemVerilog $unit Compilation Scope tutorial (Accessing It Explicitly with $unit::)	ChipVerify: SystemVerilog $unit Compilation Scope	Open
$unit Compilation Scope: Declaring Something in $unit Scope	Advanced Features	Runnable example from the SystemVerilog $unit Compilation Scope tutorial (Declaring Something in $unit Scope)	ChipVerify: SystemVerilog $unit Compilation Scope	Open
'extern': Basic Syntax	Advanced Features	Runnable example from the SystemVerilog 'extern' tutorial (Basic Syntax)	ChipVerify: SystemVerilog 'extern'	Open
'extern': Where extern Actually Earns Its Keep	Advanced Features	Runnable example from the SystemVerilog 'extern' tutorial (Where extern Actually Earns Its Keep)	ChipVerify: SystemVerilog 'extern'	Open
ANSI-C Style Declaration	Advanced Features	A function that uses the implicit return variable (sum = x + y) alongside one that uses the return keyword, plus both ways of calling them.	Ch #14: Advanced Features	Open
Functions & Tasks: Calling with Named Arguments	Advanced Features	Runnable example from the SystemVerilog Functions & Tasks tutorial (Calling with Named Arguments)	ChipVerify: SystemVerilog Functions & Tasks	Open
Functions & Tasks: Default Argument Values	Advanced Features	Runnable example from the SystemVerilog Functions & Tasks tutorial (Default Argument Values)	ChipVerify: SystemVerilog Functions & Tasks	Open
Functions & Tasks: Tasks Can Consume Time	Advanced Features	Runnable example from the SystemVerilog Functions & Tasks tutorial (Tasks Can Consume Time)	ChipVerify: SystemVerilog Functions & Tasks	Open
Functions & Tasks: const ref: Reference Efficiency Without the Mutability Risk	Advanced Features	Runnable example from the SystemVerilog Functions & Tasks tutorial (const ref: Reference Efficiency Without the Mutability Risk)	ChipVerify: SystemVerilog Functions & Tasks	Open
How To Pass Arguments By Reference?	Advanced Features	An automatic function taking a ref int argument, so changes made inside the function are visible to the caller.	Ch #14: Advanced Features	Open
How To Pass Arguments By Value?	Advanced Features	Default pass-by-value: changing the argument inside the function does not affect the caller's variable.	Ch #14: Advanced Features	Open
Nested Package Reference	Advanced Features	Chained package imports (X into Y into Z): symbols seen through one import are not automatically re-exported to the next level.	Ch #14: Advanced Features	Open
Package: Wildcard Import	Advanced Features	Runnable example from the SystemVerilog Package tutorial (Wildcard Import)	ChipVerify: SystemVerilog Package	Open
Quick Refresher: Virtual Interfaces	Advanced Features	Runnable example from the SystemVerilog Quick Refresher tutorial (Virtual Interfaces)	ChipVerify: SystemVerilog Quick Refresher	Open
Scope Resolution Operator: Accessing Static Methods and Variables	Advanced Features	Runnable example from the SystemVerilog Scope Resolution Operator tutorial (Accessing Static Methods and Variables)	ChipVerify: SystemVerilog Scope Resolution Operator	Open
Scope Resolution Operator: Defining an extern Function	Advanced Features	Runnable example from the SystemVerilog Scope Resolution Operator tutorial (Defining an extern Function)	ChipVerify: SystemVerilog Scope Resolution Operator	Open
Scope Resolution Operator: Referencing Package Members	Advanced Features	Runnable example from the SystemVerilog Scope Resolution Operator tutorial (Referencing Package Members)	ChipVerify: SystemVerilog Scope Resolution Operator	Open
Using Declarations And Directions	Advanced Features	Functions declared with separate input / output port statements, including one that returns a value while also writing an output argument.	Ch #14: Advanced Features	Open
When Accessed By Child Classes	Advanced Features	A local member of a base class is invisible even to a derived class, so the child method reading it fails to compile.	Ch #14: Advanced Features	Open
When Accessed From Outside The Class	Advanced Features	A local class member can be read inside the class's own method but not through the handle from a module, where the illegal access is flagged.	Ch #14: Advanced Features	Open
When Accessed From Outside The Class	Advanced Features	A second take on local vs public members: the local variable prints fine from inside display() but not when accessed as abc.local_var outside the class.	Ch #14: Advanced Features	Open
`define Macro: Concatenate Macros	Advanced Features	Runnable example from the SystemVerilog `define Macro tutorial (Concatenate Macros)	ChipVerify: SystemVerilog `define Macro	Open
`define Macro: SystemVerilog `define	Advanced Features	Runnable example from the SystemVerilog `define Macro tutorial (SystemVerilog `define)	ChipVerify: SystemVerilog `define Macro	Open
`define Macro: SystemVerilog `define	Advanced Features	Runnable example from the SystemVerilog `define Macro tutorial (SystemVerilog `define)	ChipVerify: SystemVerilog `define Macro	Open
`define with default arguments	Advanced Features	Runnable example from the SystemVerilog `define Macro tutorial (`define with default arguments)	ChipVerify: SystemVerilog `define Macro	Open
`define with default arguments	Advanced Features	Runnable example from the SystemVerilog `define Macro tutorial (`define with default arguments)	ChipVerify: SystemVerilog `define Macro	Open
`define without default arguments	Advanced Features	Runnable example from the SystemVerilog `define Macro tutorial (`define without default arguments)	ChipVerify: SystemVerilog `define Macro	Open
local vs protected: Accessing a protected Member From a Child Class	Advanced Features	Runnable example from the SystemVerilog local vs protected tutorial (Accessing a protected Member From a Child Class)	ChipVerify: SystemVerilog local vs protected	Open
Array Manipulation: Array Reduction Methods	Arrays	Runnable example from the SystemVerilog Array Manipulation tutorial (Array Reduction Methods)	ChipVerify: SystemVerilog Array Manipulation	Open
Array Manipulation: Mandatory 'with' Clause	Arrays	Runnable example from the SystemVerilog Array Manipulation tutorial (Mandatory 'with' Clause)	ChipVerify: SystemVerilog Array Manipulation	Open
Array Manipulation: Mandatory 'with' Clause	Arrays	Runnable example from the SystemVerilog Array Manipulation tutorial (Mandatory 'with' Clause)	ChipVerify: SystemVerilog Array Manipulation	Open
Array Manipulation: Mandatory 'with' Clause	Arrays	Runnable example from the SystemVerilog Array Manipulation tutorial (Mandatory 'with' Clause)	ChipVerify: SystemVerilog Array Manipulation	Open
Array methods example, sort by two dimensions	Arrays	Runnable example from the Systemverilog Array Manipulation tutorial.	ChipVerify: SystemVerilog Array Manipulation	Open
Arrays: Static Arrays	Arrays	Runnable example from the SystemVerilog Arrays tutorial (Static Arrays)	ChipVerify: SystemVerilog Arrays	Open
Associative Array Methods	Arrays	Runnable example from the SystemVerilog Associative Array tutorial (Associative Array Methods)	ChipVerify: SystemVerilog Associative Array	Open
Associative Array Methods Example	Arrays	Runnable example from the SystemVerilog Associative Array tutorial (Associative Array Methods Example)	ChipVerify: SystemVerilog Associative Array	Open
Associative Array: Dynamic Array Within Each Index of an Associative Array	Arrays	Runnable example from the SystemVerilog Associative Array tutorial (Dynamic Array Within Each Index of an Associative Array)	ChipVerify: SystemVerilog Associative Array	Open
Associative Array: Dynamic Array of Associative Arrays	Arrays	Runnable example from the SystemVerilog Associative Array tutorial (Dynamic Array of Associative Arrays)	ChipVerify: SystemVerilog Associative Array	Open
Associative Array: Initialization Example	Arrays	Runnable example from the SystemVerilog Associative Array tutorial (Initialization Example)	ChipVerify: SystemVerilog Associative Array	Open
Dynamic Array Example	Arrays	Runnable example from the SystemVerilog Dynamic Array tutorial (Dynamic Array Example)	ChipVerify: SystemVerilog Dynamic Array	Open
Dynamic Array Example	Arrays	Runnable example from the SystemVerilog Dynamic Array tutorial (Dynamic Array Example)	ChipVerify: SystemVerilog Dynamic Array	Open
Dynamic Array: Copying Dynamic Array Example	Arrays	Runnable example from the SystemVerilog Dynamic Array tutorial (Copying Dynamic Array Example)	ChipVerify: SystemVerilog Dynamic Array	Open
Dynamic Array: Grow and Keep Contents	Arrays	Grow a dynamic array with new[n](array) and add one more element	ChipVerify: SystemVerilog Dynamic Array	Open
Packed Array: Two-Channel Bus	Arrays	A 2D packed array holding two 8-bit channels, with per-channel and per-bit access	ChipVerify: SystemVerilog Packed Arrays	Open
Packed Arrays: Example #1	Arrays	Runnable example from the SystemVerilog Packed Arrays tutorial (Example #1)	ChipVerify: SystemVerilog Packed Arrays	Open
Packed Arrays: Example #2	Arrays	Runnable example from the SystemVerilog Packed Arrays tutorial (Example #2)	ChipVerify: SystemVerilog Packed Arrays	Open
Packed Arrays: Single Dimensional Packed Arrays	Arrays	Runnable example from the SystemVerilog Packed Arrays tutorial (Single Dimensional Packed Arrays)	ChipVerify: SystemVerilog Packed Arrays	Open
Queue Example	Arrays	Runnable example from the Systemverilog Queue tutorial.	ChipVerify: SystemVerilog Queue	Open
Queue: How to Create a Queue of Classes in SystemVerilog?	Arrays	Runnable example from the SystemVerilog Queue tutorial (How to Create a Queue of Classes in SystemVerilog?)	ChipVerify: SystemVerilog Queue	Open
Queue: How to Create a Queue of Dynamic Arrays in SystemVerilog?	Arrays	Runnable example from the SystemVerilog Queue tutorial (How to Create a Queue of Dynamic Arrays in SystemVerilog?)	ChipVerify: SystemVerilog Queue	Open
Queue: Simple FIFO Scoreboard	Arrays	Push values into a queue and pop them in order until it is empty	ChipVerify: SystemVerilog Queue	Open
Queue: SystemVerilog Queue Example	Arrays	Runnable example from the SystemVerilog Queue tutorial (SystemVerilog Queue Example)	ChipVerify: SystemVerilog Queue	Open
Queue: SystemVerilog Queue Methods Example	Arrays	Runnable example from the SystemVerilog Queue tutorial (SystemVerilog Queue Methods Example)	ChipVerify: SystemVerilog Queue	Open
Streaming Operators: Packing Values Into a Stream	Arrays	Runnable example from the SystemVerilog Streaming Operators tutorial (Packing Values Into a Stream)	ChipVerify: SystemVerilog Streaming Operators	Open
Streaming Operators: Unpacking a Stream Back Into Variables	Arrays	Runnable example from the SystemVerilog Streaming Operators tutorial (Unpacking a Stream Back Into Variables)	ChipVerify: SystemVerilog Streaming Operators	Open
Unpacked Array: Register File	Arrays	Four 16-bit registers in an unpacked array of packed elements, printed with foreach and %p	ChipVerify: SystemVerilog Unpacked Arrays	Open
Unpacked Arrays: Multidimensional Unpacked Array	Arrays	Runnable example from the SystemVerilog Unpacked Arrays tutorial (Multidimensional Unpacked Array)	ChipVerify: SystemVerilog Unpacked Arrays	Open
Unpacked Arrays: Packed + Unpacked Array	Arrays	Runnable example from the SystemVerilog Unpacked Arrays tutorial (Packed + Unpacked Array)	ChipVerify: SystemVerilog Unpacked Arrays	Open
Unpacked Arrays: Single Dimensional Unpacked Array	Arrays	Runnable example from the SystemVerilog Unpacked Arrays tutorial (Single Dimensional Unpacked Array)	ChipVerify: SystemVerilog Unpacked Arrays	Open
Immediate Assertion in Design	Assertions	Runnable example from the SystemVerilog Immediate Assertions tutorial (Immediate Assertion in Design)	ChipVerify: SystemVerilog Immediate Assertions	Open
Immediate Assertion in Testbench	Assertions	Runnable example from the SystemVerilog Immediate Assertions tutorial (Immediate Assertion in Testbench)	ChipVerify: SystemVerilog Immediate Assertions	Open
Operator	Assertions	An SVA sequence using the ##2 cycle-delay operator (a ##2 b) inside an assert property sampled on every clock edge.	Ch #9: Assertions	Open
Sequence Repetition Operator: Consecutive Repetition:	Assertions	Runnable example from the SystemVerilog Sequence Repetition Operator tutorial (Consecutive Repetition:)	ChipVerify: SystemVerilog Sequence Repetition Operator	Open
$cast As A Function	Classes & OOP	$cast used as a function - if ($cast(...)) - so an invalid value is reported and handled instead of erroring out.	Ch #5: Classes & OOP	Open
'this' keyword: The Classic Case: A Shadowed Constructor Argument	Classes & OOP	Runnable example from the SystemVerilog 'this' keyword tutorial (The Classic Case: A Shadowed Constructor Argument)	ChipVerify: SystemVerilog 'this' keyword	Open
Abstract Class Example	Classes & OOP	A virtual (abstract) class with a constructor - it cannot be instantiated directly, only its handle is used here.	Ch #5: Classes & OOP	Open
Abstract Class: A Normal Class	Classes & OOP	Runnable example from the SystemVerilog Abstract Class tutorial (A Normal Class)	ChipVerify: SystemVerilog Abstract Class	Open
Behavior Of Inherited Classes	Classes & OOP	A child new(int val = 2) that calls super.new() and then uses its argument, contrasting the default and passed-in constructor values.	Ch #5: Classes & OOP	Open
Cast Static: Bit-Width Truncation (Narrowing a Vector)	Classes & OOP	Runnable example from the SystemVerilog Cast Static tutorial (Bit-Width Truncation (Narrowing a Vector))	ChipVerify: SystemVerilog Cast Static	Open
Cast Static: Casting a String to an Integer	Classes & OOP	Runnable example from the SystemVerilog Cast Static tutorial (Casting a String to an Integer)	ChipVerify: SystemVerilog Cast Static	Open
Cast Static: Real-to-Integer Truncation	Classes & OOP	Runnable example from the SystemVerilog Cast Static tutorial (Real-to-Integer Truncation)	ChipVerify: SystemVerilog Cast Static	Open
Cast Static: Real-to-Integer Truncation	Classes & OOP	Runnable example from the SystemVerilog Cast Static tutorial (Real-to-Integer Truncation)	ChipVerify: SystemVerilog Cast Static	Open
Casting Invalid Values	Classes & OOP	$cast(myCent, 75) where 75 is not a valid enum value, so the cast fails and the target keeps its old value.	Ch #5: Classes & OOP	Open
Class Constructor: Typed Constructors	Classes & OOP	Runnable example from the SystemVerilog Class Constructor tutorial (Typed Constructors)	ChipVerify: SystemVerilog Class Constructor	Open
Class Handle: Associative Array	Classes & OOP	Runnable example from the SystemVerilog Class Handle tutorial (Associative Array)	ChipVerify: SystemVerilog Class Handle	Open
Class Handle: Dynamic Array	Classes & OOP	Runnable example from the SystemVerilog Class Handle tutorial (Dynamic Array)	ChipVerify: SystemVerilog Class Handle	Open
Class Handle: Fixed Array	Classes & OOP	Runnable example from the SystemVerilog Class Handle tutorial (Fixed Array)	ChipVerify: SystemVerilog Class Handle	Open
Class Handle: What Is a Class Handle?	Classes & OOP	Runnable example from the SystemVerilog Class Handle tutorial (What Is a Class Handle?)	ChipVerify: SystemVerilog Class Handle	Open
Class Handle: What Is a Class Handle?	Classes & OOP	Runnable example from the SystemVerilog Class Handle tutorial (What Is a Class Handle?)	ChipVerify: SystemVerilog Class Handle	Open
Class vs Struct: Assignment: Copy vs Share	Classes & OOP	Runnable example from the SystemVerilog Class vs Struct tutorial (Assignment: Copy vs Share)	ChipVerify: SystemVerilog Class vs Struct	Open
Class vs Struct: Equality: Comparing Values vs Comparing Identity	Classes & OOP	Runnable example from the SystemVerilog Class vs Struct tutorial (Equality: Comparing Values vs Comparing Identity)	ChipVerify: SystemVerilog Class vs Struct	Open
Class: How Do I Access Properties and Methods?	Classes & OOP	Runnable example from the SystemVerilog Class tutorial (How Do I Access Properties and Methods?)	ChipVerify: SystemVerilog Class	Open
Class: How Do I Create an Array of Class Objects?	Classes & OOP	Runnable example from the SystemVerilog Class tutorial (How Do I Create an Array of Class Objects?)	ChipVerify: SystemVerilog Class	Open
Const: Global Constant Class Properties	Classes & OOP	Runnable example from the SystemVerilog Const tutorial (Global Constant Class Properties)	ChipVerify: SystemVerilog Const	Open
Const: Instance Constant Class Properties	Classes & OOP	Runnable example from the SystemVerilog Const tutorial (Instance Constant Class Properties)	ChipVerify: SystemVerilog Const	Open
Copying Objects: Shallow Copy Example	Classes & OOP	Runnable example from the SystemVerilog Copying Objects tutorial (Shallow Copy Example)	ChipVerify: SystemVerilog Copying Objects	Open
Copying Objects: Shallow Copy Example	Classes & OOP	Runnable example from the SystemVerilog Copying Objects tutorial (Shallow Copy Example)	ChipVerify: SystemVerilog Copying Objects	Open
Extending Abstract Classes	Classes & OOP	A concrete ChildClass extending an abstract BaseClass and overriding the member value in its own new().	Ch #5: Classes & OOP	Open
Inheritance: A Basic Example	Classes & OOP	Runnable example from the SystemVerilog Inheritance tutorial (A Basic Example)	ChipVerify: SystemVerilog Inheritance	Open
Inheritance: Why the Handle's Type Matters (Without virtual)	Classes & OOP	Runnable example from the SystemVerilog Inheritance tutorial (Why the Handle's Type Matters (Without virtual))	ChipVerify: SystemVerilog Inheritance	Open
Parameterized Classes	Classes & OOP	A class parameterized by #(int size = 8); instances override the size and $bits() confirms the resulting widths, including a typedef alias.	Ch #5: Classes & OOP	Open
Pass Datatype As A Parameter	Classes & OOP	A class parameterized by #(type T = int) used as an int, a 4-bit vector and a real, so the same method behaves differently per type.	Ch #5: Classes & OOP	Open
Polymorphism: Assign Child Class to Base Class	Classes & OOP	Runnable example from the SystemVerilog Polymorphism tutorial (Assign Child Class to Base Class)	ChipVerify: SystemVerilog Polymorphism	Open
Pure Method Example	Classes & OOP	An abstract class with a pure virtual function that the derived class must implement before it can be used.	Ch #5: Classes & OOP	Open
Static Variables	Classes & OOP	Runnable example from the SystemVerilog Static Variables & Functions tutorial (Static Variables)	ChipVerify: SystemVerilog Static Variables & Functions	Open
Static Variables & Functions: Static Functions	Classes & OOP	Runnable example from the SystemVerilog Static Variables & Functions tutorial (Static Functions)	ChipVerify: SystemVerilog Static Variables & Functions	Open
Static Variables & Functions: The Default: Each Instance Gets Its Own Copy	Classes & OOP	Runnable example from the SystemVerilog Static Variables & Functions tutorial (The Default: Each Instance Gets Its Own Copy)	ChipVerify: SystemVerilog Static Variables & Functions	Open
Typedef Class: A Complete Working Example	Classes & OOP	Runnable example from the SystemVerilog Typedef Class tutorial (A Complete Working Example)	ChipVerify: SystemVerilog Typedef Class	Open
Using $cast	Classes & OOP	$cast(myCent, 10+5+10) converts an arithmetic result into an enum, succeeding because 25 equals QUARTER.	Ch #5: Classes & OOP	Open
Virtual Methods: Without virtual	Classes & OOP	Runnable example from the SystemVerilog Virtual Methods tutorial (Without virtual)	ChipVerify: SystemVerilog Virtual Methods	Open
Virtual Methods: Without virtual	Classes & OOP	Runnable example from the SystemVerilog Virtual Methods tutorial (Without virtual)	ChipVerify: SystemVerilog Virtual Methods	Open
When Class Constructor Is Explicity Defined	Classes & OOP	A user-defined new() initializes a member, so the object already holds that value when it is read right after new.	Ch #5: Classes & OOP	Open
When Class Constructor Is Implicitly Called	Classes & OOP	A class with no new(): the tool supplies a default constructor, so the member simply keeps its default value of 0.	Ch #5: Classes & OOP	Open
When The New Function Is Declared As Static Or Virtual	Classes & OOP	A note that a class constructor may not be virtual or static; the example just runs a plain new() that sets a string field.	Ch #5: Classes & OOP	Open
Without $cast	Classes & OOP	The same enum assignment written with $cast (a plain myCent = 25 would be illegal), contrasting the task form with the function form.	Ch #5: Classes & OOP	Open
super Keyword: Accessing an Overridden Base Method With super	Classes & OOP	Runnable example from the SystemVerilog super Keyword tutorial (Accessing an Overridden Base Method With super)	ChipVerify: SystemVerilog super Keyword	Open
Array Reduction Iterative Constraint	Constraints	An array-reduction constraint, array.sum() with (int'(item)) == 20, forcing the elements to add up to 20.	Ch #7: Constraints	Open
Bus Protocol Constraints	Constraints	Simple example on how to create a bus transaction object	Ch#7 : Constraints	Open
Constraint 'inside': Practical Example	Constraints	Runnable example from the SystemVerilog Constraint 'inside' tutorial (Practical Example)	ChipVerify: SystemVerilog Constraint 'inside'	Open
Constraint Blocks: Simple Constraint Block	Constraints	Runnable example from the SystemVerilog Constraint Blocks tutorial (Simple Constraint Block)	ChipVerify: SystemVerilog Constraint Blocks	Open
Constraint Examples: :/ Operator	Constraints	Runnable example from the SystemVerilog Constraint Examples tutorial (:/ Operator)	ChipVerify: SystemVerilog Constraint Examples	Open
Constraint Examples: := Operator	Constraints	Runnable example from the SystemVerilog Constraint Examples tutorial (:= Operator)	ChipVerify: SystemVerilog Constraint Examples	Open
Constraint Examples: Bidirectional Constraints	Constraints	Runnable example from the SystemVerilog Constraint Examples tutorial (Bidirectional Constraints)	ChipVerify: SystemVerilog Constraint Examples	Open
Disable Constraints Example 1	Constraints	constraint_mode() called as a function to query whether the c_num constraint is enabled before randomizing.	Ch #7: Constraints	Open
Disable Constraints Example 2	Constraints	c_num.constraint_mode(0) disables a constraint so randomize() ignores its range on num.	Ch #7: Constraints	Open
Equal Memory Partitions	Constraints	Shows how to create equal regions in memory using constraints and randomization	Ch#7 : Constraints	Open
How Is It Different From Hard Constraints?	Constraints	The same code with a hard range constraint, so randomize() with { data == 2; } conflicts and randomization fails.	Ch #7: Constraints	Open
Implication Constraint Example 1	Constraints	An implication constraint mode == 2 -> len > 10: the consequent is enforced only when the antecedent holds, otherwise len is free.	Ch #7: Constraints	Open
Implication Constraint Example 2	Constraints	An implication constraint with a range antecedent - mode inside {[5:B]} -> mod_en == 1.	Ch #7: Constraints	Open
Implication Constraint Example 3	Constraints	A constraint that uses if/else (with a nested if/else in braces) to set mod_en according to which range mode falls in.	Ch #7: Constraints	Open
Inline Constraints: Basic Inline Constraint	Constraints	Runnable example from the SystemVerilog Inline Constraints tutorial (Basic Inline Constraint)	ChipVerify: SystemVerilog Inline Constraints	Open
Inline Constraints: Basic Inline Constraint	Constraints	Runnable example from the SystemVerilog Inline Constraints tutorial (Basic Inline Constraint)	ChipVerify: SystemVerilog Inline Constraints	Open
Inverted Inside	Constraints	A negated inside constraint, !(m_var inside {[3:7]}), forces the randomized value to fall outside 3 to 7.	Ch #7: Constraints	Open
Memory Block Randomization	Constraints	Shows how constraints can be used to reserve a region in memory	Ch#7 : Constraints	Open
Multidimensional Arrays	Constraints	A nested foreach constraint over a packed multidimensional array, forcing even indices to 'hF and odd indices to 0.	Ch #7: Constraints	Open
Multidimensional Dynamic Arrays	Constraints	A foreach constraint that fixes the outer size first, then randomizes each inner sub-array's size and element values.	Ch #7: Constraints	Open
Non-static Constraints	Constraints	Two ordinary non-static constraints on a class; two objects then randomize independently of each other.	Ch #7: Constraints	Open
Partition For Programs And Data	Constraints	A memory-layout class that splits RAM into program, data and free regions using size lists, dist weighting and a total-size sum() constraint.	Ch #7: Constraints	Open
Soft Constraints Example	Constraints	A soft constraint (soft data >= 4) that is silently dropped when an inline randomize() with { data == 2; } contradicts it.	Ch #7: Constraints	Open
Turn Off Non-static Constraint	Constraints	One plain constraint and one static constraint; disabling the non-static one on obj1 affects only that object.	Ch #7: Constraints	Open
Turn Off Static Constraint	Constraints	Disabling a static constraint through one handle turns it off for every object of the class.	Ch #7: Constraints	Open
Used In Constraints	Constraints	A class constraint m_var inside {[3:7]} keeps the randomized value between 3 and 7 across repeated randomize() calls.	Ch #7: Constraints	Open
Variable Memory Partitions	Constraints	Shows how to create memory regions of different sizes	Ch#7 : Constraints	Open
Variable Memory Partitions With Space In Between	Constraints	A RAM-partitioning class: constraints choose a partition count, per-partition sizes and inter-partition gaps that fill the address range, then derive each start…	Ch #7: Constraints	Open
When Used In Conditional Statements	Constraints	The inside operator used in a ternary and in if/else to test whether a random value falls in the range 4 to 9.	Ch #7: Constraints	Open
With Solve - Before	Constraints	The same constraint plus solve a before b, biasing the solver to pick a first so a == 1 occurs about half the time.	Ch #7: Constraints	Open
Without Solve - Before	Constraints	The constraint a -> b == 3 with no solve order, so the joint solution makes a == 0 far more likely.	Ch #7: Constraints	Open
external constraints	Constraints	Runnable example from the Systemverilog Constraint Blocks tutorial.	ChipVerify: SystemVerilog Constraint Blocks	Open
foreach Constraint Example 1	Constraints	A foreach constraint that sets every element of a fixed array equal to its own index.	Ch #7: Constraints	Open
foreach Constraint Example 2	Constraints	foreach constraints on both a dynamic array and a queue, with the queue sized by a separate constraint and the dynamic array sized in new().	Ch #7: Constraints	Open
solve before: Random Distribution Example	Constraints	Runnable example from the SystemVerilog solve before tutorial (Random Distribution Example)	ChipVerify: SystemVerilog solve before	Open
'break' and 'continue': break	Control Flow & Loops	Runnable example from the SystemVerilog 'break' and 'continue' tutorial (break)	ChipVerify: SystemVerilog 'break' and 'continue'	Open
'break' and 'continue': break	Control Flow & Loops	Runnable example from the SystemVerilog 'break' and 'continue' tutorial (break)	ChipVerify: SystemVerilog 'break' and 'continue'	Open
'break' and 'continue': break in Nested Loops	Control Flow & Loops	Runnable example from the SystemVerilog 'break' and 'continue' tutorial (break in Nested Loops)	ChipVerify: SystemVerilog 'break' and 'continue'	Open
'unique' and 'priority' case: unique: No items match for given expression	Control Flow & Loops	Runnable example from the SystemVerilog 'unique' and 'priority' case tutorial (unique: No items match for given expression)	ChipVerify: SystemVerilog 'unique' and 'priority' case	Open
'unique' and 'priority' if-else: Exit after first match in priority-if	Control Flow & Loops	Runnable example from the SystemVerilog 'unique' and 'priority' if-else tutorial (Exit after first match in priority-if)	ChipVerify: SystemVerilog 'unique' and 'priority' if-else	Open
'unique' and 'priority' if-else: No else clause in priority-if	Control Flow & Loops	Runnable example from the SystemVerilog 'unique' and 'priority' if-else tutorial (No else clause in priority-if)	ChipVerify: SystemVerilog 'unique' and 'priority' if-else	Open
Design Example	Control Flow & Loops	A parameterized priority encoder driven by a for-loop testbench that walks one-hot inputs and checks the priority cases.	Ch #4: Control Flow & Loops	Open
Do While Loop	Control Flow & Loops	A do...while loop that still executes its body once even though the while condition is false from the start.	Ch #4: Control Flow & Loops	Open
Do While Loop	Control Flow & Loops	A do...while loop that runs once and then continues while cnt < 5.	Ch #4: Control Flow & Loops	Open
Exit After First Match In Priority-if	Control Flow & Loops	priority if evaluates its conditions in order and executes only the first one that matches.	Ch #4: Control Flow & Loops	Open
Forever	Control Flow & Loops	A forever loop that prints every 5ns, kept from hanging the simulation by a separate initial block that calls $finish at 50ns.	Ch #4: Control Flow & Loops	Open
Loops: foreach	Control Flow & Loops	Runnable example from the SystemVerilog Loops tutorial (foreach)	ChipVerify: SystemVerilog Loops	Open
Loops: forever	Control Flow & Loops	Runnable example from the SystemVerilog Loops tutorial (forever)	ChipVerify: SystemVerilog Loops	Open
Loops: repeat	Control Flow & Loops	Runnable example from the SystemVerilog Loops tutorial (repeat)	ChipVerify: SystemVerilog Loops	Open
Loops: while	Control Flow & Loops	Runnable example from the SystemVerilog Loops tutorial (while)	ChipVerify: SystemVerilog Loops	Open
Loops: while	Control Flow & Loops	Runnable example from the SystemVerilog Loops tutorial (while)	ChipVerify: SystemVerilog Loops	Open
Loops: while	Control Flow & Loops	Runnable example from the SystemVerilog Loops tutorial (while)	ChipVerify: SystemVerilog Loops	Open
Multidimensional Arrays	Control Flow & Loops	Nested foreach (md_array[i]) / foreach (md_array[i][j]) to walk a 5 by 2 array.	Ch #4: Control Flow & Loops	Open
Multiple Matches In Unique-if	Control Flow & Loops	A unique if where two branch conditions are both true, which triggers a uniqueness violation.	Ch #4: Control Flow & Loops	Open
No Else Block For Unique-if	Control Flow & Loops	A unique if with an else runs cleanly; a second unique if with no else and no matching branch reports a violation.	Ch #4: Control Flow & Loops	Open
No Else Clause In Priority-if	Control Flow & Loops	A priority if with an else is fine; without an else and with no match it reports a violation.	Ch #4: Control Flow & Loops	Open
Priority Case	Control Flow & Loops	A priority case with duplicate items executes only the first matching branch and reports no violation.	Ch #4: Control Flow & Loops	Open
Repeat	Control Flow & Loops	A repeat(5) loop that executes its block exactly five times and exits.	Ch #4: Control Flow & Loops	Open
Single Dimensional Arrays	Control Flow & Loops	foreach over a fixed array to print its elements and, in a second loop, accumulate their running sum.	Ch #4: Control Flow & Loops	Open
Unique: More Than One Case Item Matches	Control Flow & Loops	A unique case with a duplicate matching item (0 listed twice), which reports a violation.	Ch #4: Control Flow & Loops	Open
Unique: No Items Match For Given Expression	Control Flow & Loops	A unique case where no case item matches the selector, which reports a violation.	Ch #4: Control Flow & Loops	Open
While And Do-While Loop Example	Control Flow & Loops	A while loop whose condition is already false on entry, so the body never runs.	Ch #4: Control Flow & Loops	Open
While Loop	Control Flow & Loops	A while loop counting from 0 to 4.	Ch #4: Control Flow & Loops	Open
for loop: Using the for Loop in Verification	Control Flow & Loops	Runnable example from the SystemVerilog for loop tutorial (Using the for Loop in Verification)	ChipVerify: SystemVerilog for loop	Open
for loop: Using the for Loop in Verification	Control Flow & Loops	Runnable example from the SystemVerilog for loop tutorial (Using the for Loop in Verification)	ChipVerify: SystemVerilog for loop	Open
for loop: Using the for Loop in Verification	Control Flow & Loops	Runnable example from the SystemVerilog for loop tutorial (Using the for Loop in Verification)	ChipVerify: SystemVerilog for loop	Open
foreach loop: Example #1: Single-Dimensional Arrays	Control Flow & Loops	Runnable example from the SystemVerilog foreach loop tutorial (Example #1: Single-Dimensional Arrays)	ChipVerify: SystemVerilog foreach loop	Open
foreach loop: Example #2: Multidimensional Arrays	Control Flow & Loops	Runnable example from the SystemVerilog foreach loop tutorial (Example #2: Multidimensional Arrays)	ChipVerify: SystemVerilog foreach loop	Open
foreach loop: Example #2: Multidimensional Arrays	Control Flow & Loops	Runnable example from the SystemVerilog foreach loop tutorial (Example #2: Multidimensional Arrays)	ChipVerify: SystemVerilog foreach loop	Open
foreach loop: Iteration Order	Control Flow & Loops	Runnable example from the SystemVerilog foreach loop tutorial (Iteration Order)	ChipVerify: SystemVerilog foreach loop	Open
foreach loop: Using foreach in Verification	Control Flow & Loops	Runnable example from the SystemVerilog foreach loop tutorial (Using foreach in Verification)	ChipVerify: SystemVerilog foreach loop	Open
forever loop: Example: A Testbench Monitor	Control Flow & Loops	Runnable example from the SystemVerilog forever loop tutorial (Example: A Testbench Monitor)	ChipVerify: SystemVerilog forever loop	Open
forever loop: Example: Clock Generation	Control Flow & Loops	Runnable example from the SystemVerilog forever loop tutorial (Example: Clock Generation)	ChipVerify: SystemVerilog forever loop	Open
forever loop: Stopping a forever Loop	Control Flow & Loops	Runnable example from the SystemVerilog forever loop tutorial (Stopping a forever Loop)	ChipVerify: SystemVerilog forever loop	Open
repeat: Example #1: Repeat a Statement	Control Flow & Loops	Runnable example from the SystemVerilog repeat tutorial (Example #1: Repeat a Statement)	ChipVerify: SystemVerilog repeat	Open
repeat: Example #2: Wait for N Clock Cycles	Control Flow & Loops	Runnable example from the SystemVerilog repeat tutorial (Example #2: Wait for N Clock Cycles)	ChipVerify: SystemVerilog repeat	Open
repeat: Using repeat in Verification	Control Flow & Loops	Runnable example from the SystemVerilog repeat tutorial (Using repeat in Verification)	ChipVerify: SystemVerilog repeat	Open
while and do-while loop: Example #1: while Loop	Control Flow & Loops	Runnable example from the SystemVerilog while and do-while loop tutorial (Example #1: while Loop)	ChipVerify: SystemVerilog while and do-while loop	Open
while and do-while loop: Example #2: while Loop That Never Runs	Control Flow & Loops	Runnable example from the SystemVerilog while and do-while loop tutorial (Example #2: while Loop That Never Runs)	ChipVerify: SystemVerilog while and do-while loop	Open
while and do-while loop: Example #3: do while Loop	Control Flow & Loops	Runnable example from the SystemVerilog while and do-while loop tutorial (Example #3: do while Loop)	ChipVerify: SystemVerilog while and do-while loop	Open
while and do-while loop: Example #3: do while Loop	Control Flow & Loops	Runnable example from the SystemVerilog while and do-while loop tutorial (Example #3: do while Loop)	ChipVerify: SystemVerilog while and do-while loop	Open
while and do-while loop: Using while in Verification: Polling with a Timeout	Control Flow & Loops	Runnable example from the SystemVerilog while and do-while loop tutorial (Using while in Verification: Polling with a Timeout)	ChipVerify: SystemVerilog while and do-while loop	Open
Associative Array Iterators	Data Types	Simple examples of associative array methods	ChipVerify Ch#3 Assoc Arrays	Open
Associative Array Methods	Data Types	How to use in-built methods of associative arrays		Open
Associative Arrays	Data Types	Create and display associative arrays where keys and values are of different types: https://www.chipverify.com/systemverilog/systemverilog-associative-array		Open
Copy Dynamic Array	Data Types	How to copy dynamic arrays		Open
Data Types: Fixed Arrays	Data Types	Runnable example from the SystemVerilog Data Types tutorial (Fixed Arrays)	ChipVerify: SystemVerilog Data Types	Open
Data Types: Floating Point/Exponential Numbers	Data Types	Runnable example from the SystemVerilog Data Types tutorial (Floating Point/Exponential Numbers)	ChipVerify: SystemVerilog Data Types	Open
Dynamic Array Methods	Data Types	How to use in-built methods of dynamic arrays		Open
Dynamic Arrays	Data Types	Create and iterate a dynamic array : https://www.chipverify.com/systemverilog/systemverilog-dynamic-array		Open
Dynamic array inside Associative arrays	Data Types	How to create and iterate a dynamic array as a value for each key in an associative array		Open
Dynamic array of Associative arrays	Data Types	How to create multiple associative arrays and store them inside a dynamic array		Open
Enhanced Literal	Data Types	Example of how ' literal can be used to assign full 1s	Ch#2 : Data Types	Open
Enumeration Example	Data Types	Every enum numbering style in one file: implicit, explicit values, name[N], name[N]=C, name[N:M], and name[N:M]=C.	Ch #2: Data Types	Open
Enumeration Methods Example	Data Types	The enum methods first(), last(), next(), prev(), num() and name() demonstrated on a colors variable.	Ch #2: Data Types	Open
Fill Literals: '0 and '1	Data Types	Unbased unsized fill literals set every bit of a vector regardless of its width	ChipVerify: SystemVerilog Data Types	Open
How To Define A New Enumerated Data Type?	Data Types	typedef enum {NO, YES} boolean defines a new type; a variable of it is assigned and printed with .name.	Ch #2: Data Types	Open
Multidimensional Unpacked Array	Data Types	Example of a simple MDA : https://www.chipverify.com/systemverilog/systemverilog-unpacked-arrays		Open
Queue Indexing	Data Types	Example on accessing queue with indices		Open
Queue Methods	Data Types	Simple code on how to use queue methods		Open
Queue of Classes	Data Types	Create, iterate and print a queue of class objects		Open
Queue of Dynamic Arrays	Data Types	Create, iterate and print a queue of dynamic arrays		Open
Queues	Data Types	Simple introduction to SV Queues, see more at https://www.chipverify.com/systemverilog/systemverilog-queue		Open
Single Dimensional Unpacked Array	Data Types	Example of a regular array		Open
Strings Example	Data Types	Runnable example from the Systemverilog Strings tutorial.	ChipVerify: SystemVerilog Strings	Open
Strings Example	Data Types	Runnable example from the Systemverilog Strings tutorial.	ChipVerify: SystemVerilog Strings	Open
Strings: SystemVerilog String Example	Data Types	Runnable example from the SystemVerilog Strings tutorial (SystemVerilog String Example)	ChipVerify: SystemVerilog Strings	Open
Structure Comparison With Union	Data Types	Compare how struct behaves with union	Ch #2: Data Types	Open
Structure Example	Data Types	An anonymous struct variable initialized with '{...}, printed with %p, then updated member by member.	Ch #2: Data Types	Open
Structure Example	Data Types	A packed struct mapped onto an 8-bit register: initialize by field list, change one field, then assign a raw 8-bit value to the whole struct.	Ch #2: Data Types	Open
Structure: Array of Structures	Data Types	Runnable example from the SystemVerilog Structure tutorial (Array of Structures)	ChipVerify: SystemVerilog Structure	Open
SystemVerilog Union	Data Types		Ch #2: Data Types	Open
Type Checking	Data Types	Enum strict typing: a direct integer assignment is illegal, an explicit e_light'(1) cast is legal, and the enum auto-casts to int inside comparisons.	Ch #2: Data Types	Open
Typedef Alias Example	Data Types	Runnable example from the Systemverilog Typedef Alias tutorial.	ChipVerify: SystemVerilog typedef and alias	Open
What Is The Need To Typedef A Structure?	Data Types	typedef struct makes a reusable type; assigning one struct variable to another copies by value, so changing the source leaves the copy untouched.	Ch #2: Data Types	Open
bit, byte and int: 2-State Data Types	Data Types	Runnable example from the SystemVerilog bit, byte and int tutorial (2-State Data Types)	ChipVerify: SystemVerilog bit, byte and int	Open
bit, byte and int: Data Types Integer Byte Example	Data Types	Runnable example from the Systemverilog Data Types Integer Byte tutorial.	ChipVerify: SystemVerilog bit, byte and int	Open
bit, byte and int: Sign Cast	Data Types	Runnable example from the SystemVerilog bit, byte and int tutorial (Sign Cast)	ChipVerify: SystemVerilog bit, byte and int	Open
bit, byte and int: bit datatype	Data Types	Runnable example from the Systemverilog Data Types Integer Byte tutorial.	ChipVerify: SystemVerilog bit, byte and int	Open
bit, byte and int: byte	Data Types	Runnable example from the SystemVerilog bit, byte and int tutorial (byte)	ChipVerify: SystemVerilog bit, byte and int	Open
bit, byte and int: int	Data Types	Runnable example from the SystemVerilog bit, byte and int tutorial (int)	ChipVerify: SystemVerilog bit, byte and int	Open
bit, byte and int: longint	Data Types	Runnable example from the SystemVerilog bit, byte and int tutorial (longint)	ChipVerify: SystemVerilog bit, byte and int	Open
bit, byte and int: shortint	Data Types	Runnable example from the SystemVerilog bit, byte and int tutorial (shortint)	ChipVerify: SystemVerilog bit, byte and int	Open
logic: Example 1: Driven from Both a Procedural Block and a Continuous Assign	Data Types	Runnable example from the SystemVerilog logic tutorial (Example 1: Driven from Both a Procedural Block and a Continuous Assign)	ChipVerify: SystemVerilog logic	Open
logic: Example 2: Driven Purely from a Procedural Block	Data Types	Runnable example from the SystemVerilog logic tutorial (Example 2: Driven Purely from a Procedural Block)	ChipVerify: SystemVerilog logic	Open
logic: Example 3: Driven Purely from a Continuous Assign	Data Types	Runnable example from the SystemVerilog logic tutorial (Example 3: Driven Purely from a Continuous Assign)	ChipVerify: SystemVerilog logic	Open
FV ALU vs Reference Model (with a bug)	Formal Verification	An 8-bit ALU whose set-less-than compares unsigned. One assertion against a reference model finds it.	Formal Verification tutorial: Datapaths Against a Reference Model	Open
FV APB Register Block (with a bug)	Formal Verification	A write to the read-only ID register at 0xC also lands in the scratch register. Found with read-after-write.	Formal Verification tutorial: Simple Bus Slave	Open
FV Adder RTL vs Netlist (with a wrong gate)	Formal Verification	A 4-bit adder, its gate netlist with one hand-edited gate, and a miter that asserts equal outputs.	Formal Verification tutorial: Combinational Equivalence	Open
FV Arbiter Starvation (with a bug)	Formal Verification	A fixed-priority arbiter that starves requester 1. Bounded liveness req[1] \|-> ##[0:4] gnt[1] finds it.	Formal Verification tutorial: Safety and Liveness	Open
FV Assume-Guarantee: source and sink	Formal Verification	The source proves its guarantees; the sink assumes them and proves the sum. Set the top module to src, then to sink.	Formal Verification tutorial: Assume-Guarantee	Open
FV Bug Hunt: five designs	Formal Verification	Five small designs, each with one bug. Select a top module, write one property in its FORMAL block, and find the bug.	Formal Verification tutorial: Bug Hunt	Open
FV Capstone: UART transmitter (with a bug)	Formal Verification	A parameterized UART transmitter checked against a reference timeline with a symbolic bit index. It sends the data bits in the wrong order.	Formal Verification tutorial: Capstone: UART Transmitter	Open
FV Capstone: prove a FIFO	Formal Verification	A complete FIFO check with flags, tracked-value order and three helper invariants. Run the base case, then the induction step.	Formal Verification tutorial: Capstone: Verify a FIFO	Open
FV Capstone: round-robin arbiter	Formal Verification	The fixed round-robin arbiter with safety, fairness and a hold assumption; covers as commented meant-to-fail checks.	Formal Verification tutorial: Capstone: Verify a Round-Robin Arbiter	Open
FV Cone of Influence: control vs data	Formal Verification	The shift-and-add multiplier with only its control property. Fast at any width, because the datapath is outside the cone.	Formal Verification tutorial: State Explosion	Open
FV Counter 0 to 5 (with a bug)	Formal Verification	A counter that should count from 0 to 5 wraps at 6; the formal check finds it. Fix the wrap value.	Formal Verification tutorial: What Is Formal Verification?	Open
FV Coverage Closure: classify the holes	Formal Verification	Four simulation coverage holes of the request controller as meant-to-fail checks. Activate them one at a time.	Formal Verification tutorial: Formal for Coverage Closure	Open
FV Covers for a State Machine	Formal Verification	One cover per state and one for an err/stop collision. The collision is unreachable because of a priority bug.	Formal Verification tutorial: Cover Properties as a Sanity Check	Open
FV Debouncer: choosing a depth (with a bug)	Formal Verification	A debouncer that waits one cycle too long. Depths 5 and 6 pass, depth 7 finds the bug.	Formal Verification tutorial: Choosing a Depth	Open
FV Debugging a Non-Equivalence	Formal Verification	The adder miter with a different wrong gate in the netlist. Localize the difference from the counterexample.	Formal Verification tutorial: When Equivalence Fails	Open
FV Decimal Counter: bounded pass or proof?	Formal Verification	A mod-10 counter with the rule q <= 9. The normal run is the base case; the induction step is included as a comment.	Formal Verification tutorial: Why a Passing BMC Is Not a Proof	Open
FV Decimal Counter: the induction step	Formal Verification	The induction step for q <= 9 with K = 1, run in the lab. Change the property to q != 11 to see a false step failure.	Formal Verification tutorial: Induction: Base Case and Step	Open
FV FIFO Counter (with a bug)	Formal Verification	The occupancy counter of a 4-entry FIFO goes up to 5. Read the counterexample, find the bug and fix it.	Formal Verification tutorial: Reading a Counterexample	Open
FV FIFO Data Integrity (with a bug)	Formal Verification	A 4-entry FIFO whose write pointer does not move on a simultaneous push and pop. The tracked (magic) value finds the lost word.	Formal Verification tutorial: Data Integrity Properties	Open
FV FIFO: shrinking the problem	Formal Verification	A parameterized FIFO with flag and tracked-value checks. Change W (data bits) and AW (address bits) to see the run time change.	Formal Verification tutorial: Shrinking the Problem	Open
FV Formal Wrapper (formal_props.sv)	Formal Verification	The saturating counter checked from outside through a formal_props.sv wrapper, without editing the design file.	Formal Verification tutorial: The ifdef FORMAL Block and the Formal Wrapper	Open
FV Interrupt Controller: symbolic channel (with a bug)	Formal Verification	One property for a channel the tool chooses covers all eight channels and finds the one that loses interrupts.	Formal Verification tutorial: Symbolic Values	Open
FV Job Unit Latency (with a bug)	Formal Verification	A unit with 1-cycle and 3-cycle jobs; the long job takes 4. The SVA window start \|-> ##[1:3] done, written with a helper counter.	Formal Verification tutorial: Sequences and Implication	Open
FV LFSR: distance from reset	Formal Verification	A 16-bit LFSR that never reaches zero. Change the asserted value to measure how many cycles a state is from reset.	Formal Verification tutorial: How BMC Unrolls a Design	Open
FV Lockstep Counters: induction fails	Formal Verification	Two identical counters always agree, but the induction step fails from an unreachable start state.	Formal Verification tutorial: Unreachable States and Induction Failures	Open
FV Lockstep Counters: strengthened	Formal Verification	The induction step with the helper invariant a == b passes with K = 1.	Formal Verification tutorial: Strengthening Invariants	Open
FV MAC with a Cut Point	Formal Verification	A multiply-accumulate unit. Define CUT_MULT to replace the multiplier with a free value and see a false failure.	Formal Verification tutorial: Black Boxes and Cut Points	Open
FV Magic Value: Left-Over Debug Code	Formal Verification	An alarm that must never be raised hides behind one 32-bit value; random simulation almost never finds it, formal does in a few cycles.	Formal Verification tutorial: Formal vs Simulation	Open
FV Mod-60 Counter: a deep bug	Formal Verification	The bug needs 62 cycles to show. Passes at depth 10, fails at depth 63 (PRO). Scale it down with a parameter to find it on the free tier.	Formal Verification tutorial: Depth, Engines and Limits	Open
FV One-Hot Multiplexer: why assumptions	Formal Verification	An AND-OR multiplexer that is correct only for one-hot selects. Remove the assumption to see a false failure.	Formal Verification tutorial: Why Assumptions Are Needed	Open
FV Over-Constrained Check (hides a bug)	Formal Verification	A tracker with an off-by-one limit. An assumption that is too strong makes everything pass; find and remove it.	Formal Verification tutorial: Over-Constraining	Open
FV Pin Multiplexer: connectivity and reset (with a bug)	Formal Verification	A 4-pad pin multiplexer checked against its connectivity table and reset values. One pad is missing from the reset.	Formal Verification tutorial: Connectivity and Reset Checks	Open
FV Pointer FIFO (with a bug)	Formal Verification	A 4-entry FIFO that reports full after 3 words. A reference count checks the flags against the specified depth.	Formal Verification tutorial: Synchronous FIFOs	Open
FV Priority Arbiter (with a bug)	Formal Verification	A 4-requester fixed-priority arbiter that can grant two requesters at once. A $onehot0 invariant finds it.	Formal Verification tutorial: Invariants	Open
FV Proof in Two Halves	Formal Verification	Base case and induction step for the lockstep counters, selected with a `define switch. Both must pass.	Formal Verification tutorial: Proofs in Practice	Open
FV Pulse Timer: assert, assume, cover	Formal Verification	A timer that is busy for 3 cycles. Passes with the assumption "no start while busy"; remove it to see the counterexample.	Formal Verification tutorial: assert, assume and cover	Open
FV Register File with x0 (with a bug)	Formal Verification	Register 0 should always read as zero, but it is a real register. Read-after-write is checked with a tracked register.	Formal Verification tutorial: Register Files and Memories	Open
FV Request Controller FSM (with a bug)	Formal Verification	A controller with a 4-cycle timeout whose timer is not cleared on a new request.	Formal Verification tutorial: Finite State Machines	Open
FV Restating the RTL	Formal Verification	The buggy FIFO counter with two properties: one copied from the RTL (passes) and one from the specification (fails).	Formal Verification tutorial: Writing Good Properties	Open
FV Round-Robin Arbiter (with a bug)	Formal Verification	A 4-requester round-robin arbiter whose pointer never moves. The fairness check finds a starving requester.	Formal Verification tutorial: Arbiters	Open
FV Saturating Adder (with a bug)	Formal Verification	An 8-bit saturating adder that misses some overflows. An immediate and a clocked assertion find it in the first step.	Formal Verification tutorial: Immediate and Concurrent Assertions	Open
FV Saturating Counter	Formal Verification	A counter that stops at 12. Two assertions: never above 12, and stays at 12. Passes; try depth 20 with PRO.	Formal Verification tutorial: Your First Formal Run	Open
FV Shift-and-Add Multiplier: run time	Formal Verification	A W-bit sequential multiplier checked against a*b. Fast at 6 bits, 15 s at 8 bits, over 300 s at 10 bits.	Formal Verification tutorial: Performance	Open
FV Skid Buffer (with a bug)	Formal Verification	A skid buffer that sends a word twice when a new word arrives while the old one leaves.	Formal Verification tutorial: Valid/Ready Pipelines and Skid Buffers	Open
FV Source and Sink: debugging a counterexample	Formal Verification	An end-to-end sum check across two modules fails. Localize the cause with a boundary assertion and a hypothesis.	Formal Verification tutorial: Debugging Counterexamples Efficiently	Open
FV Sticky Error Flag (with a bug)	Formal Verification	An error flag that should stay set until cleared but forgets the error. Checked with $past, $rose and $fell.	Formal Verification tutorial: $past, $rose, $fell and $stable	Open
FV Tick Divider (with a bug)	Formal Verification	A divide-by-3 tick that comes every 4 cycles. The period property finds the off-by-one wrap.	Formal Verification tutorial: Counters and Clock Dividers	Open
FV Traffic Light: Reachable States	Formal Verification	A 2-bit state machine with three states; prove that the unused encoding 11 is never reached from reset.	Formal Verification tutorial: State and Reachability	Open
FV Traffic Light: binary vs one-hot (with a bug)	Formal Verification	Sequential equivalence of two encodings of the same state machine, with a bug in the one-hot version.	Formal Verification tutorial: Sequential Equivalence	Open
FV Transaction Tracker: protocol assumption	Formal Verification	Counts requests in flight to a memory. Passes with the assumption "responses only for requests in flight"; remove it to see the count wrap.	Formal Verification tutorial: Input Protocol Assumptions	Open
FV Vacuous Property (with a bug)	Formal Verification	A state machine with a bug and a property whose trigger can never happen. Everything passes until the trigger is fixed.	Formal Verification tutorial: Vacuity	Open
FV Valid Pipeline: a missing reset	Formal Verification	A two-stage pipeline whose second valid bit is not reset; a word appears right after reset.	Formal Verification tutorial: Reset and Initial State	Open
FV Valid/Ready Sender (with a bug)	Formal Verification	A stream sender that changes its data while the receiver is not ready. The handshake rules find it.	Formal Verification tutorial: Handshake Properties	Open
FV Watchdog: a deep bug	Formal Verification	A watchdog that wraps after 1023 cycles. Passes at depth 100 from reset; start anywhere to find it in two steps.	Formal Verification tutorial: Deep Bugs	Open
FV X-Propagation: two copies (with a bug)	Formal Verification	Two copies of a pipeline with independent start values: after reset their outputs must agree. Also a decoder with an unreachable branch (top dec_dead).	Formal Verification tutorial: X-Propagation and Unreachable Code	Open
Automatic Bins	Functional Coverage	A coverpoint using bins range[] = {[0:$]} to auto-create one bin per possible value of the sampled variable.	Ch #8: Functional Coverage	Open
Covergroup	Functional Coverage	A covergroup sampled on posedge clk with a single coverpoint on a 2-bit variable; instantiated like a class object, with get_inst_coverage() printed at the end …	Ch #8: Functional Coverage	Open
Coverpoint	Functional Coverage	One covergroup holding several named coverpoints - a plain variable, two bit-selects of another, and an expression - all sampled together on the clock edge.	Ch #8: Functional Coverage	Open
Coverpoint Bins Example	Functional Coverage	A coverpoint with two explicit single-value bins (bins one = {1}, bins five = {5}), sampled manually with cg_inst.sample().	Ch #8: Functional Coverage	Open
Fixed Number Of Automatic Bins	Functional Coverage	bins range[4] = {[0:$]} splits the full value range into exactly four bins.	Ch #8: Functional Coverage	Open
Split Fixed Number Of Bins Between A Given Range	Functional Coverage	bins range[3] = {[1:4], 7} distributes the listed values across three bins.	Ch #8: Functional Coverage	Open
Clocking Blocks Part 1: Declaring a Clocking Block Inside an Interface	Interfaces & Modports	Runnable example from the SystemVerilog Clocking Blocks Part 1 tutorial (Declaring a Clocking Block Inside an Interface)	ChipVerify: SystemVerilog Clocking Blocks Part 1	Open
Clocking Blocks Part 2: A Complete Example	Interfaces & Modports	Runnable example from the SystemVerilog Clocking Blocks Part 2 tutorial (A Complete Example)	ChipVerify: SystemVerilog Clocking Blocks Part 2	Open
Clocking Blocks Part 2: Input Skew in Detail	Interfaces & Modports	Runnable example from the SystemVerilog Clocking Blocks Part 2 tutorial (Input Skew in Detail)	ChipVerify: SystemVerilog Clocking Blocks Part 2	Open
Clocking Blocks Part 2: Output Skew in Detail	Interfaces & Modports	Runnable example from the SystemVerilog Clocking Blocks Part 2 tutorial (Output Skew in Detail)	ChipVerify: SystemVerilog Clocking Blocks Part 2	Open
Interface With A SystemVerilog Design	Interfaces & Modports	The same counter, but the DUT takes the interface directly as a port and drives _if.count, and the interface itself carries an init() task.	Ch #10: Interfaces & Modports	Open
Interface With A Verilog Design	Interfaces & Modports	A SystemVerilog interface bundles a counter's signals while the plain-Verilog DUT is still connected port by port from that interface.	Ch #10: Interfaces & Modports	Open
Interface: How Do You Connect an Interface to a DUT?	Interfaces & Modports	Runnable example from the SystemVerilog Interface tutorial (How Do You Connect an Interface to a DUT?)	ChipVerify: SystemVerilog Interface	Open
Modport Example	Interfaces & Modports	An interface with modport slave and modport master; master and slave modules take their modport views and are joined in a top module driven by the testbench.	Ch #10: Interfaces & Modports	Open
Virtual Interface: A Complete Example	Interfaces & Modports	Runnable example from the SystemVerilog Virtual Interface tutorial (A Complete Example)	ChipVerify: SystemVerilog Virtual Interface	Open
Event Example	Interprocess Communication	One event triggered with -> and waited on three ways in parallel: @(event) and wait(event.triggered).	Ch #12: Interprocess Communication	Open
Event: How to Trigger and Wait for an Event	Interprocess Communication	Runnable example from the SystemVerilog Event tutorial (How to Trigger and Wait for an Event)	ChipVerify: SystemVerilog Event	Open
Generic Mailbox Example	Interprocess Communication	A bounded mailbox of capacity 2 with a producer putting one item per ns and a consumer taking one every 2ns, printing num() as it fills and drains.	Ch #12: Interprocess Communication	Open
Interprocess Communication: What Are Events?	Interprocess Communication	Runnable example from the SystemVerilog Interprocess Communication tutorial (What Are Events?)	ChipVerify: SystemVerilog Interprocess Communication	Open
Interprocess Communication: What's a Mailbox?	Interprocess Communication	Runnable example from the SystemVerilog Interprocess Communication tutorial (What's a Mailbox?)	ChipVerify: SystemVerilog Interprocess Communication	Open
Interprocess Communication: What's a Semaphore?	Interprocess Communication	Runnable example from the SystemVerilog Interprocess Communication tutorial (What's a Semaphore?)	ChipVerify: SystemVerilog Interprocess Communication	Open
Mailbox Example	Interprocess Communication	A parameterized mailbox #(string) shared between two class components by handle assignment; one puts strings, the other loops on get().	Ch #12: Interprocess Communication	Open
Mailbox: peek() and try_peek(): Looking Without Removing	Interprocess Communication	Runnable example from the SystemVerilog Mailbox tutorial (peek() and try_peek(): Looking Without Removing)	ChipVerify: SystemVerilog Mailbox	Open
Mailbox: try_put(): Checking for Room Without Blocking	Interprocess Communication	Runnable example from the SystemVerilog Mailbox tutorial (try_put(): Checking for Room Without Blocking)	ChipVerify: SystemVerilog Mailbox	Open
Matching Different Type Mailboxes	Interprocess Communication	A mailbox #(string) handle assigned into a mailbox #(byte) handle, showing the type mismatch between parameterized mailboxes.	Ch #12: Interprocess Communication	Open
Merging Events	Interprocess Communication	Reassigning one event handle to another at run time (event_b = event_a) so a wait on event_b is satisfied when event_a triggers.	Ch #12: Interprocess Communication	Open
Semaphore: A Basic Example: Mutual Exclusion With One Key	Interprocess Communication	Runnable example from the SystemVerilog Semaphore tutorial (A Basic Example: Mutual Exclusion With One Key)	ChipVerify: SystemVerilog Semaphore	Open
Semaphore: A Semaphore With Multiple Keys	Interprocess Communication	Runnable example from the SystemVerilog Semaphore tutorial (A Semaphore With Multiple Keys)	ChipVerify: SystemVerilog Semaphore	Open
Semaphore: try_get(): Checking for a Key Without Waiting	Interprocess Communication	Runnable example from the SystemVerilog Semaphore tutorial (try_get(): Checking for a Key Without Waiting)	ChipVerify: SystemVerilog Semaphore	Open
Wait_order	Interprocess Communication	wait_order(a, b, c) passes only when the three events fire in that exact sequence, with an else branch for the wrong order.	Ch #12: Interprocess Communication	Open
What Is The Difference Between @ And.triggered?	Interprocess Communication	The same event, but each waiter first delays #20 - showing @(event) misses an already-fired trigger while .triggered still sees it.	Ch #12: Interprocess Communication	Open
Interview Questions Set 4: How to find indices associated with associative array	Interview Questions	Runnable example from the SystemVerilog Interview Questions Set 4 tutorial (How to find indices associated with associative array items?)	ChipVerify: SystemVerilog Interview Questions Set 4	Open
Interview Questions Set 4: Is it possible to override existing constraints?	Interview Questions	Runnable example from the SystemVerilog Interview Questions Set 4 tutorial (Is it possible to override existing constraints?)	ChipVerify: SystemVerilog Interview Questions Set 4	Open
Interview Questions Set 5: How to disable randomization?	Interview Questions	Runnable example from the SystemVerilog Interview Questions Set 5 tutorial (How to disable randomization?)	ChipVerify: SystemVerilog Interview Questions Set 5	Open
Interview Questions Set 5: Write a constraint to detect odd numbers of ones in a	Interview Questions	Runnable example from the SystemVerilog Interview Questions Set 5 tutorial (Write a constraint to detect odd numbers of ones in an 8-bit sequence.)	ChipVerify: SystemVerilog Interview Questions Set 5	Open
Interview Questions Set 6: Randomly generate 8, 16, 32, 64 with equal probabilit	Interview Questions	Runnable example from the SystemVerilog Interview Questions Set 6 tutorial (Randomly generate 8, 16, 32, 64 with equal probability using SystemVerilog construct…	ChipVerify: SystemVerilog Interview Questions Set 6	Open
Interview Questions Set 7: Write SV code to wait for a random delay in range 100	Interview Questions	Runnable example from the SystemVerilog Interview Questions Set 7 tutorial (Write SV code to wait for a random delay in range 100 to 500 ns.)	ChipVerify: SystemVerilog Interview Questions Set 7	Open
Interview Questions Set 8: Constrain a dynamic array such that it does not pick	Interview Questions	Runnable example from the SystemVerilog Interview Questions Set 8 tutorial (Constrain a dynamic array such that it does not pick values from another array.)	ChipVerify: SystemVerilog Interview Questions Set 8	Open
Interview Questions Set 9: How to generate array without randomization?	Interview Questions	Runnable example from the SystemVerilog Interview Questions Set 9 tutorial (How to generate array without randomization?)	ChipVerify: SystemVerilog Interview Questions Set 9	Open
Interview Questions Set 9: Write randomization constraints for the following req	Interview Questions	Runnable example from the SystemVerilog Interview Questions Set 9 tutorial (Write randomization constraints for the following requirements on an array.)	ChipVerify: SystemVerilog Interview Questions Set 9	Open
TestBench: What Are Abstraction Levels?	Introduction & Basics	Runnable example from the SystemVerilog TestBench tutorial (What Are Abstraction Levels?)	ChipVerify: SystemVerilog TestBench	Open
After Using Rand_mode()	Randomization	f.rand_mode(0) called on the object turns off randomization for all of its rand variables at once.	Ch #6: Randomization	Open
After Using Rand_mode()	Randomization	var1.rand_mode(0) turns off randomization for one variable, so it keeps its value while the others still randomize.	Ch #6: Randomization	Open
Disable Randomization: Randomization Enabled by Default	Randomization	Runnable example from the SystemVerilog Disable Randomization tutorial (Randomization Enabled by Default)	ChipVerify: SystemVerilog Disable Randomization	Open
Dynamic Array Randomization	Randomization	How to randomize a dynamic array. Note : Verilator fails to handle this code properly ! But it works on commercial grade simulators like Xcelium, VCS, etc.		Open
Dynamic Array Randomization in a Class	Randomization	A rand dynamic array with size and per-element foreach constraints (d_array[i] == i).	Ch #6: Randomization	Open
How Is Randomization Done In SystemVerilog?	Randomization	A class with rand and randc variables plus range constraints, randomized 15 times with assert(randomize()) to show randc cycling through every value before repe…	Ch #6: Randomization	Open
Queue Randomization	Randomization	A rand queue inside a class constrained to size() == 4 and then randomized.	Ch #6: Randomization	Open
Random: rand: Uniformly Distributed, Repeats Allowed	Randomization	Runnable example from the SystemVerilog Random tutorial (rand: Uniformly Distributed, Repeats Allowed)	ChipVerify: SystemVerilog Random	Open
Random: randc: Cycles Through Every Value Before Repeating	Randomization	Runnable example from the SystemVerilog Random tutorial (randc: Cycles Through Every Value Before Repeating)	ChipVerify: SystemVerilog Random	Open
Randomization: Always Check the Return Value	Randomization	Runnable example from the SystemVerilog Randomization tutorial (Always Check the Return Value)	ChipVerify: SystemVerilog Randomization	Open
Randomizing Class Properties	Randomization	Runnable example from the SystemVerilog Randomization tutorial (Randomizing Class Properties)	ChipVerify: SystemVerilog Randomization	Open
Randomizing Plain Variables with std::randomize()	Randomization	Runnable example from the SystemVerilog Randomization tutorial (Randomizing Plain Variables with std::randomize())	ChipVerify: SystemVerilog Randomization	Open
Static Array Randomization	Randomization	How to randomize a static array		Open
Static Arrays	Randomization	A rand fixed-size array inside a class, randomized and printed with %p.	Ch #6: Randomization	Open
Without Using Rand_mode()	Randomization	rand_mode() queried as a function to confirm that randomization is enabled for the class's variables.	Ch #6: Randomization	Open
pre_randomize & post_randomize: Calling randomize()	Randomization	Runnable example from the SystemVerilog pre_randomize & post_randomize tutorial (Calling randomize())	ChipVerify: SystemVerilog pre_randomize & post_randomize	Open
randcase: Weighted Random Branch Selection	Randomization	Runnable example from the SystemVerilog randcase tutorial (Weighted Random Branch Selection)	ChipVerify: SystemVerilog randcase	Open
randcase: Weighted Random Branch Selection	Randomization	Runnable example from the SystemVerilog randcase tutorial (Weighted Random Branch Selection)	ChipVerify: SystemVerilog randcase	Open
#0 Delay: The Gotcha: #0 Still Runs Before NBA	Scheduling Semantics	Runnable example from the SystemVerilog #0 Delay tutorial (The Gotcha: #0 Still Runs Before NBA)	ChipVerify: SystemVerilog #0 Delay	Open
Delta Cycles: Multi-Level Combinational Logic Needs Multiple Delta Cycles	Scheduling Semantics	Runnable example from the SystemVerilog Delta Cycles tutorial (Multi-Level Combinational Logic Needs Multiple Delta Cycles)	ChipVerify: SystemVerilog Delta Cycles	Open
Command Line Arguments: $test$plusargs: Checking Whether an Argument Was Passed	Testbench Components	Runnable example from the SystemVerilog Command Line Arguments tutorial ($test$plusargs: Checking Whether an Argument Was Passed)	ChipVerify: SystemVerilog Command Line Arguments	Open
Command Line Arguments: $value$plusargs: Extracting a Value	Testbench Components	Runnable example from the SystemVerilog Command Line Arguments tutorial ($value$plusargs: Extracting a Value)	ChipVerify: SystemVerilog Command Line Arguments	Open
File Operations Example 1	Testbench Components	$fopen in read versus write mode, checking the returned file descriptor each time, then $fclose.	Ch #13: Testbench Components	Open
File Operations Example 2	Testbench Components	Opening the same file with w, r and a modes into separate descriptors and checking each one.	Ch #13: Testbench Components	Open
File Operations Example 3	Testbench Components	Writing five lines with $fdisplay, then reopening the file and reading them back line by line with $fgets.	Ch #13: Testbench Components	Open
File Operations Example 4	Testbench Components	The same file write, then reading until $feof in a while loop with $fgets.	Ch #13: Testbench Components	Open
File Operations Example 5	Testbench Components	The same file write, then parsing each line with $fscanf("%s = %0d", ...) and using its match count as the loop condition.	Ch #13: Testbench Components	Open
Simple Memory Testbench Example	Testbench Components	Runnable example from the Systemverilog Testbench Example 1 tutorial.	ChipVerify: SystemVerilog Testbench Example 1	Open
Testbench Example Adder	Testbench Components	Runnable example from the Systemverilog Testbench Example Adder tutorial.	ChipVerify: SystemVerilog Testbench Example Adder	Open
Testbench Top	Testbench Components	A complete class-based (non-UVM) testbench for a packet switch: generator, driver, semaphore-pipelined monitor, and a scoreboard that checks address routing.	Ch #13: Testbench Components	Open
file operations: What Are Multichannel File Descriptors?	Testbench Components	Runnable example from the SystemVerilog file operations tutorial (What Are Multichannel File Descriptors?)	ChipVerify: SystemVerilog file operations	Open
Does Wait Fork Wait Until All Processes Are Over?	Threads & Processes	A second fork...join_any followed by wait fork, showing wait fork waits for all outstanding sub-threads, not only the current fork.	Ch #11: Threads & Processes	Open
Fork Join Example	Threads & Processes	Another fork...join with three parallel threads of different delays; the parent prints only after the longest one ends.	Ch #11: Threads & Processes	Open
Fork Join Example	Threads & Processes	Three statements run in parallel inside fork...join; the parent thread resumes only after all three have finished.	Ch #11: Threads & Processes	Open
Fork Join Example 1	Threads & Processes	A fork...join nested inside another fork...join, using an automatic task so each spawned copy keeps its own arguments.	Ch #11: Threads & Processes	Open
Fork Join Example 2	Threads & Processes	A fork...join whose first branch is itself a fork...join of three delayed threads, showing how the nested join holds the parent until every leaf finishes.	Ch #11: Threads & Processes	Open
Fork Join_any Example	Threads & Processes	fork...join_any: the parent resumes as soon as the first of three parallel threads completes, leaving the others running.	Ch #11: Threads & Processes	Open
Fork Join_any Example	Threads & Processes	fork...join_any with an automatic task: the parent resumes after the first thread (the 10-unit one) completes.	Ch #11: Threads & Processes	Open
Fork Join_none Example	Threads & Processes	fork...join_none: the parent continues immediately without waiting for any spawned thread.	Ch #11: Threads & Processes	Open
Nested Fork Join_any	Threads & Processes	join_any nested inside join_any, so the inner join releasing its parent lets the outer join release as well.	Ch #11: Threads & Processes	Open
Nested Fork Join_none	Threads & Processes	join_none nested inside another join_none - neither level blocks, so every print happens after the parent has already finished.	Ch #11: Threads & Processes	Open
Process Class: A Complete Example	Threads & Processes	Runnable example from the SystemVerilog Process Class tutorial (A Complete Example)	ChipVerify: SystemVerilog Process Class	Open
Wait Fork Example	Threads & Processes	wait fork placed after a join_any makes the parent block until every thread spawned in that fork has finished.	Ch #11: Threads & Processes	Open
What Happens When Fork Is Disabled?	Threads & Processes	Adding disable fork after a join_any kills the still-running sibling threads so their later prints never happen.	Ch #11: Threads & Processes	Open
Why Disable A Fork?	Threads & Processes	fork...join_any where the parent proceeds after the first thread, but the remaining threads keep running and still print later.	Ch #11: Threads & Processes	Open
Why Do We Need Automatic Task?	Threads & Processes	The same join_none fork calling a static task, so all threads share one copy of the arguments and print the wrong names - the case that motivates automatic.	Ch #11: Threads & Processes	Open
disable: A Basic Example: Disabling One Named Block	Threads & Processes	Runnable example from the SystemVerilog disable tutorial (A Basic Example: Disabling One Named Block)	ChipVerify: SystemVerilog disable	Open
fork join_none: Forking Inside a Loop	Threads & Processes	Runnable example from the SystemVerilog fork join_none tutorial (Forking Inside a Loop)	ChipVerify: SystemVerilog fork join_none	Open
fork join_none: Forking Inside a Loop	Threads & Processes	Runnable example from the SystemVerilog fork join_none tutorial (Forking Inside a Loop)	ChipVerify: SystemVerilog fork join_none	Open

UVM

35 examples

Name	Topic	Description	Reference	Open
AHB Sequence		A UVM AHB-Lite master agent with a burst-aware packet whose post_randomize() computes INCR/WRAP addresses per beat, driven by a base test and sequence.	UVM	Open
Factory Methods		UVM example from the ChipVerify tutorial: Factory Methods.	UVM	Open
Object Pack and Unpack		UVM example from the ChipVerify tutorial: Object Pack and Unpack.	UVM	Open
Simple Memory Testbench Example 1		UVM example from the ChipVerify tutorial: Simple Memory Testbench Example 1.	UVM	Open
TLM FIFO Crossing Hierarchies		UVM example from the ChipVerify tutorial: TLM FIFO Crossing Hierarchies.	UVM	Open
TLM FIFO Example		UVM example from the ChipVerify tutorial: TLM FIFO Example.	UVM	Open
TLM Port to Export Crossing Hierarchy		UVM example from the ChipVerify tutorial: TLM Port to Export Crossing Hierarchy.	UVM	Open
TLM Put Port to Export to Imp		UVM example from the ChipVerify tutorial: TLM Put Port to Export to Imp.	UVM	Open
TLM Put Port to Port to Export to Export to Imp		UVM example from the ChipVerify tutorial: TLM Put Port to Port to Export to Export to Imp.	UVM	Open
TLM Put Port to Port to Imp		UVM example from the ChipVerify tutorial: TLM Put Port to Port to Imp.	UVM	Open
Testbench Top		A reusable UVM APB master agent - config, packet, driver, monitor, sequencer - plus a base test, sequence and scoreboard driving the APB interface.	UVM	Open
Testbench for a 2-Port Switch		UVM example from the ChipVerify tutorial: Testbench for a 2-Port Switch.	UVM	Open
Define The Test Class	Advanced Topics	A minimal UVM environment - sequence item, driver, sequencer, sequence, test - wired so the driver pulls one item with get_next_item() / item_done().	Ch #12: Advanced Topics	Open
Define The Test Class	Advanced Topics	A UVM environment where the driver and sequence use blocking get() / put() with get_response(), instead of get_next_item(), showing the response handshake.	Ch #12: Advanced Topics	Open
Example Of Backdoor Access In Sequence	Register Model (RAL)	A UVM RAL sequence that reads and writes registers through backdoor HDL-path access instead of driving bus cycles.	Ch #11: Register Model (RAL)	Open
Register Model Example	Register Model (RAL)	A full UVM register-model (RAL) example over an APB-style bus: a reg_rw_test does front-door reads and writes to a traffic-light controller's registers.	Ch #11: Register Model (RAL)	Open
Case #1: Wait_trigger -> Trigger	Reporting & Utilities	uvm_event: process_b is already blocked on wait_trigger() when process_a fires trigger() at #100, so process_b unblocks.	Ch #10: Reporting & Utilities	Open
Case #2: Trigger -> Wait_trigger	Reporting & Utilities	uvm_event: process_a triggers immediately, then process_b calls wait_trigger() #100 later and blocks forever because the trigger was already missed.	Ch #10: Reporting & Utilities	Open
Case #3: Trigger & Wait_trigger At Same Time	Reporting & Utilities	uvm_event: both processes run with no delay, so whether wait_trigger() catches the trigger depends on scheduling order within the same time step.	Ch #10: Reporting & Utilities	Open
Case #3: Wait_ptrigger -> Trigger	Reporting & Utilities	uvm_event with wait_ptrigger() and process_a triggering at #100: the persistent variant unblocks the already-waiting process_b.	Ch #10: Reporting & Utilities	Open
Case #4: Trigger -> Wait_ptrigger	Reporting & Utilities	uvm_event where trigger() happens first and wait_ptrigger() runs #100 later: unlike wait_trigger(), the persistent trigger is still seen.	Ch #10: Reporting & Utilities	Open
Case #6: Trigger & Wait_ptrigger At Same Time	Reporting & Utilities	uvm_event where both processes delay #100 then trigger and wait_ptrigger() in the same step; the persistent trigger makes the wait deterministic.	Ch #10: Reporting & Utilities	Open
Usecase Example	Reporting & Utilities	uvm_event_pool: an agent registers a reset event in the global pool with add(), and the env retrieves it with get_global() to react to resets.	Ch #10: Reporting & Utilities	Open
Nonblocking Behavior	TLM (Transaction Level Modeling)	A nonblocking try_put() wrapped in a retry loop (or a can_put() poll) so the sender effectively blocks until the receiver is ready.	Ch #7: TLM (Transaction Level Modeling)	Open
UVM TLM Get Port Example	TLM (Transaction Level Modeling)	Two UVM components joined by a blocking uvm_get_port / uvm_get_imp; componentB calls get() and componentA returns a freshly randomized packet.	Ch #7: TLM (Transaction Level Modeling)	Open
UVM TLM Nonblocking Get Example	TLM (Transaction Level Modeling)	A nonblocking uvm_get_port where componentB uses try_get() (optionally polling can_get() with a dist) to pull packets without consuming time.	Ch #7: TLM (Transaction Level Modeling)	Open
UVM TLM Nonblocking Put Example	TLM (Transaction Level Modeling)	A nonblocking uvm_put_port where componentA calls try_put() and acts on its boolean return instead of blocking.	Ch #7: TLM (Transaction Level Modeling)	Open
UVM TLM Port Example	TLM (Transaction Level Modeling)	Two UVM components joined by a blocking uvm_put_port / uvm_put_imp; componentA calls put() and componentB implements it, optionally with a processing delay.	Ch #7: TLM (Transaction Level Modeling)	Open
Using Clone Method	UVM Base Classes	A UVM object with do_copy() used via clone(), which allocates a new object and copies into it in a single call.	Ch #3: UVM Base Classes	Open
Using Convert2string	UVM Base Classes	A UVM object that supplies its own convert2string() (and do_print) to format its fields, called from the test after randomize.	Ch #3: UVM Base Classes	Open
Using Do_compare	UVM Base Classes	A UVM object overriding do_compare() to check its fields (and a nested object) one by one, exercised as the test copies a single field at a time.	Ch #3: UVM Base Classes	Open
Using Do_copy	UVM Base Classes	A UVM object overriding do_copy() to deep-copy each field, including a nested object, when obj2.copy(obj1) is called.	Ch #3: UVM Base Classes	Open
Verification Testbench Example	UVM Examples	A full UVM testbench for a 1011 sequence-detector FSM, with BUG_FIX_* macros in the DUT and a scoreboard that shifts inputs and predicts out.	Ch #14: UVM Examples	Open
Automatic Objection Handling In Sequences	UVM Phases	The same sequence using set_automatic_phase_objection(1) so UVM raises and drops the phase objection for it automatically.	Ch #5: UVM Phases	Open
Explicitly Raising An Objection Within The Sequence's Task	UVM Phases	A UVM sequence that fetches its phase with get_starting_phase() and calls raise_objection / drop_objection itself around its stimulus.	Ch #5: UVM Phases	Open

Computer Architecture

1 example

Name	Topic	Description	Reference	Open
Boot C on a RISC-V Core	Computer Architecture	Compile C for RISC-V and boot it on an editable cvr32 core. Press Run Simulation: the program prints to the Console and every pipeline signal appears in the wav…	Computer Architecture tutorial	Open

SoC Design

2 examples

Name	Topic	Description	Reference	Open
SoC Design: Boot C on cvsoc	SoC Design	Compile C for RISC-V and boot it on cvsoc: the cvr32 core with a TCM, an AXI4-Lite interconnect, SRAM, UART, timer and GPIO. All the RTL is here to read and cha…	SoC Design tutorial	Open
SoC Design: cvsoc Reference SoC	SoC Design	cvsoc version 0: the cvr32 core with a 64 KB TCM, an AXI4-Lite interconnect, 16 KB system SRAM and UART, timer and GPIO on APB. Runtime Args: +workload=NAME (he…	SoC Design tutorial	Open

Code Examples

SoC Design: Boot C on cvsoc

Verilog

SystemVerilog

UVM

Computer Architecture

SoC Design