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STA Chain: Clock Skew Between Two Flip-Flops

Verilog Static Timing Analysis

Two flip-flops with a logic cone between them that fails setup at 1.0 ns; delay the capture clock to fix it

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Related tutorial:
design.v
module sta_chain (input clk, input a, b, c, d, e, output q);
  reg r1, r2;
  always @(posedge clk)
    r1 <= a;
  wire w = (((r1 ^ b) & c) ^ (d | e)) & (r1 | d);
  always @(posedge clk)
    r2 <= w;
  assign q = r2;
endmodule
constraints.sdc
# Run synthesis first, then STA. With PRO you can edit this file and run STA again without synthesis,
# and pick another library and corner in the drop-down.
create_clock -name clk -period 1.0 [get_ports clk]
set_input_delay  0.2 -clock clk [get_ports {a b c d e}]
set_output_delay 0.2 -clock clk [get_ports q]

# Exercise: delay the clock of the capturing flip-flop (find its name in the report; _11_ in our run).
# set_clock_latency 0.1 [get_pins _11_/CLK]
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