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STA DDR Input: Both Clock Edges

Verilog Static Timing Analysis

Data that changes on both edges of the clock needs an input delay for each edge

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Related tutorial:
design.v
module sta_ddr (input clk, d, output q0, q1);
  reg rp, rn;
  always @(posedge clk)
    rp <= d;
  always @(negedge clk)
    rn <= d;
  assign q0 = rp;
  assign q1 = rn;
endmodule
constraints.sdc
# Run synthesis first, then STA. With PRO you can edit this file and run STA again without synthesis,
# and pick another library and corner in the drop-down.
create_clock -name clk -period 2.0 [get_ports clk]
set_input_delay 0.3 -clock clk [get_ports d]
set_output_delay 0.2 -clock clk [get_ports {q0 q1}]

# Exercise: add the second input delay (falling-edge data). Without it only half of the data is described.
# set_input_delay 0.3 -clock clk -clock_fall -add_delay [get_ports d]
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