module sta_demo (input clk, input a, b, c, d, output y, z);
  reg r1, r2;
  always @(posedge clk) r1 <= a & b;     // input -> register
  always @(posedge clk) r2 <= r1 ^ c;    // register -> register (c: input -> register)
  assign y = r1 & r2;                    // register -> output
  assign z = a | d;                      // input -> output
endmodule

# Run synthesis first, then STA. With PRO you can edit this file and run STA again without synthesis,
# and pick another library and corner in the drop-down.
create_clock -name clk -period 2.0 [get_ports clk]
set_input_delay  0.4 -clock clk [get_ports {a b c d}]
set_output_delay 0.4 -clock clk [get_ports {y z}]

# ---- Lines used by the exercises of the tutorial. Remove the # to try one. ----
# Instance names such as _7_ and _6_ come from synthesis. Check them in your own report.
# set_clock_uncertainty 0.5 [get_clocks clk]
# set_clock_latency 0.3 [get_clocks clk]
# set_clock_latency -source 0.5 [get_clocks clk]
# set_load 0.02 [get_ports z]
# set_input_transition 1.0 [get_ports c]
# set_output_delay 1.0 -clock clk [get_ports y]
# set_case_analysis 0 [get_ports b]
# set_multicycle_path 3 -setup -from [get_pins _7_/CLK] -to [get_pins _6_/D]
# set_max_delay 0.5 -from [get_ports a] -to [get_ports z]
# set_max_transition 0.05 [current_design]
# report_check_types -max_slew -violators -digits 4
# check_setup -verbose