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STA Clock Divider and Generated Clock

Verilog Static Timing Analysis

A divide-by-2 flip-flop makes a clock that STA does not know until you define it as a generated clock

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design.v
module sta_div (input clk, input d, output q);
  reg div, r, s;
  initial div = 1'b0;
  always @(posedge clk) div <= ~div;
  always @(posedge div) r <= d;
  always @(posedge clk) s <= r;
  assign q = s;
endmodule
constraints.sdc
# Run synthesis first, then STA. With PRO you can edit this file and run STA again without synthesis,
# and pick another library and corner in the drop-down.
create_clock -name clk -period 2.0 [get_ports clk]
set_input_delay  0.4 -clock clk [get_ports d]
set_output_delay 0.4 -clock clk [get_ports q]

# Exercise: define the divided clock (the divider flip-flop was _4_ in our run, check yours).
# create_generated_clock -name clk_div -source [get_ports clk] -divide_by 2 [get_pins _4_/Q]
# set_clock_uncertainty 0.1 -from [get_clocks clk_div] -to [get_clocks clk] -setup
# check_setup -verbose
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