module tb;
  reg        clk = 0;
  reg        wr_en;
  reg  [7:0] wr_addr, wr_data;

  always #5 clk = ~clk;

  // Drive one write transaction: one clock cycle with wr_en high
  task write_reg (input [7:0] addr, input [7:0] data);
    begin
      @(posedge clk);          // Wait for a clock edge: allowed in a task
      wr_en   <= 1'b1;         // Drive module-level signals directly
      wr_addr <= addr;
      wr_data <= data;
      @(posedge clk);
      wr_en   <= 1'b0;         // End of the transaction
    end
  endtask

  initial begin
    wr_en = 0;
    write_reg(8'h10, 8'hA5);   // Each call takes two clock cycles
    write_reg(8'h14, 8'h3C);
    #20 $finish;
  end
endmodule